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mb/google/zork: update berknip CHTC thermal setting 

Update APU CHTC thermal temperature protection point:
Temperature limit(C'): 90

Update system config=2 to meet TDP 15W design.

BUG=b:162377903
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check CHTC temperature by AMD utility

Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kevin Chiu 2020-11-03 15:28:22 +08:00 committed by Felix Held
parent 9065f4f8ed
commit d029a579ba
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/zork/variants/berknip/overridetree.cb
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@ -6,7 +6,7 @@ chip soc/amd/picasso
# For the below fields, 0 indicates use SOC default # For the below fields, 0 indicates use SOC default
# System config index # System config index
register "system_config" = "3" register "system_config" = "2"
# Set STAPM confiuration. All of these fields must be set >0 to take affect # Set STAPM confiuration. All of these fields must be set >0 to take affect
register "slow_ppt_limit_mW" = "20000" register "slow_ppt_limit_mW" = "20000"
@ -14,6 +14,7 @@ chip soc/amd/picasso
register "slow_ppt_time_constant_s" = "5" register "slow_ppt_time_constant_s" = "5"
register "stapm_time_constant_s" = "200" register "stapm_time_constant_s" = "200"
register "sustained_power_limit_mW" = "12000" register "sustained_power_limit_mW" = "12000"
register "thermctl_limit_degreeC" = "90"
register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_slope_mA" = "65599"
register "telemetry_vddcr_vdd_offset" = "0" register "telemetry_vddcr_vdd_offset" = "0"