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nb/intel/ironlake: Drop `heci_bar` field from raminit 

This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.

Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-09-14 18:42:12 +02:00
parent 122e4ebd7d
commit d02f3303d9
1 changed files with 1 additions and 7 deletions
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8
src/northbridge/intel/ironlake/raminit.c
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@ -61,7 +61,7 @@ typedef struct {
u8 largest;
} timing_bounds_t[2][2][2][9];
#define MRC_CACHE_VERSION 1
#define MRC_CACHE_VERSION 2
struct ram_training {
/* [TM][CHANNEL][SLOT][RANK][LANE] */
@ -192,7 +192,6 @@ struct raminfo {
unsigned int interleaved_part_mb;
unsigned int non_interleaved_part_mb;
u32 heci_bar;
u64 heci_uma_addr;
unsigned int memory_reserved_for_heci_mb;
@ -1469,9 +1468,6 @@ static void collect_system_info(struct raminfo *info)
while (!(read8((u8 *)0xfed40000) & (1 << 7)))
;
if (!info->heci_bar)
gav(info->heci_bar =
pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
if (!info->memory_reserved_for_heci_mb) {
/* Wait for ME to be ready */
intel_early_me_init();
@ -1817,7 +1813,6 @@ static void setup_heci_uma(struct raminfo *info)
if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20)))
return;
info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0;
info->memory_reserved_for_heci_mb = reg44 & 0x3f;
info->heci_uma_addr =
((u64)
@ -3727,7 +3722,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
info.training.reg_178 = 0;
info.training.reg_10b = 0;
info.heci_bar = 0;
info.memory_reserved_for_heci_mb = 0;
/* before SPD */