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intel/i440bx: Implement EARLY_CBMEM_INIT support 

Implement cbmem_top() required for cbmem support in romstage.
Boot tested on asus/p2b-ls. Boards to move to this setup in
followup patches.

Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20977
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Keith Hui 2017-09-02 18:13:11 -04:00 committed by Kyösti Mälkki
parent 82fbb1cf55
commit d0301c1a01
3 changed files with 68 additions and 1 deletions
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2
src/northbridge/intel/i440bx/Makefile.inc
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@ -17,8 +17,10 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
ramstage-y += northbridge.c
ramstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c
romstage-y += raminit.c
romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
romstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c
endif

3
src/northbridge/intel/i440bx/northbridge.c
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@ -67,7 +67,8 @@ static void i440bx_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
set_late_cbmem_top(tomk * 1024);
if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
set_late_cbmem_top(tomk * 1024);
}
assign_resources(dev->link_list);
}

64
src/northbridge/intel/i440bx/ram_calc.c Normal file
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@ -0,0 +1,64 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Keith Hui <buurin@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include "i440bx.h"
void *cbmem_top(void)
{
/* Base of TSEG is top of usable DRAM */
/*
* SMRAM - System Management RAM Control Register
* 0x72
* [7:4] Not relevant to this function.
* [3:3] Global SMRAM Enable (G_SMRAME)
* [2:0] Hardwired to 010.
*
* ESMRAMC - Extended System Management RAM Control
* 0x73
* [7:7] H_SMRAM_EN
* 1 = When G_SMRAME=1, High SMRAM space is enabled at
* 0x100A0000-0x100FFFFF and forwarded to DRAM address
* 0x000A0000-0x000FFFFF.
* 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at
* 0x000A0000-0x000BFFFF.
* [6:3] Not relevant to this function.
* [2:1] TSEG Size (T_SZ)
* Selects the size of the TSEG memory block, if enabled.
* 00 = 128KiB
* 01 = 256KiB
* 10 = 512KiB
* 11 = 1MiB
* [0:0] TSEG_EN
* When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to
* appear between DRAM address (TOM-<TSEG Size>) to TOM.
*
* Source: 440BX datasheet, pages 3-28 thru 3-29.
*/
unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB;
int gsmrame = pci_read_config8(NB, SMRAM) & 0x8;
/* T_SZ and TSEG_EN */
int tseg = pci_read_config8(NB, ESMRAMC) & 0x7;
if ((tseg & 0x1) && gsmrame) {
int tseg_size = 128 * KiB * (1 << (tseg >> 1));
tom -= tseg_size;
}
return (void *)tom;
}