From d03e896b57ea1ae2fea640937df2d57b684ce629 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 21 Oct 2022 11:09:27 +0200 Subject: [PATCH] soc/intel/eklhartlake: Provide an option to disable the L1 prefetcher Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. In the end, this will result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/soc/intel/elkhartlake/chip.h | 3 +++ src/soc/intel/elkhartlake/cpu.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index d63844ffe7..94a2cdff78 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -454,6 +454,9 @@ struct soc_intel_elkhartlake_config { * 3600, 3733, 4000, 4200, 4267 and 0 for Auto. */ uint16_t max_dram_speed_mts; + + /* Disable L1 prefetcher */ + bool L1_prefetcher_disable; }; typedef struct soc_intel_elkhartlake_config config_t; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index f4baa65fd9..8ba28c0159 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -67,6 +67,14 @@ static void configure_misc(void) msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 23); /* Lock it */ wrmsr(MSR_POWER_CTL, msr); + + /* In some cases it is beneficial for the performance to disable the + L1 prefetcher as on Elkhart Lake it is set up a bit too aggressive. */ + if (conf->L1_prefetcher_disable) { + msr = rdmsr(MSR_PREFETCH_CTL); + msr.lo |= PREFETCH_L1_DISABLE; + wrmsr(MSR_PREFETCH_CTL, msr); + } } /* All CPUs including BSP will run the following function. */