nb/intel/sandybridge/raminit: Add ECC debug code
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -416,10 +416,41 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
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set_scrambling_seed(&ctrl);
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if (!s3resume && ctrl.ecc_enabled)
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channel_scrub(&ctrl);
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set_normal_operation(&ctrl);
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final_registers(&ctrl);
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/* can't do this earlier because it needs to be done in normal operation */
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if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) {
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uint32_t i, tseg = pci_read_config32(HOST_BRIDGE, TSEGMB);
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printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n",
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tseg);
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/*
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* This test helps to debug the ECC scrubbing.
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* It likely tests every channel/rank, as rank interleave and enhanced
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* interleave are enabled, but there's no guarantee for it.
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*/
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/* Skip first MB to avoid special case for A-seg and test up to TSEG */
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for (i = 1; i < tseg >> 20; i++) {
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for (int j = 0; j < 1 * MiB; j += 4096) {
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uintptr_t addr = i * MiB + j;
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if (read32((u32 *)addr) == 0)
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continue;
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printk(BIOS_ERR, "RAMINIT: ECC scrub: DRAM not cleared at"
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" addr 0x%lx\n", addr);
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break;
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}
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}
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printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n");
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}
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/* Zone config */
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dram_zones(&ctrl, 0);
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@ -687,9 +687,6 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_
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err = channel_test(ctrl);
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if (err)
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return err;
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if (ctrl->ecc_enabled)
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channel_scrub(ctrl);
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}
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/* Set MAD-DIMM registers */
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