mb/intel/tglrvp: Add support for USB Type-C connector device properties

This change updates TGLRVP configuration to have USB Type-C connector
device properties filled into ACPI SSDT.

TEST=Built and booted to kernel on tglrvp boards. Verified the USBC
scope under LPCB.EC0.CREC with required connector device properties.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ifd4c59afb3b8a222598fd4ff36d72c4b877bdad2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/intel/tglrvp/Makefile.inc

@@ -14,6 +14,7 @@ romstage-y += board_id.c
 smm-y += smihandler.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
 ramstage-y += mainboard.c
 ramstage-y += board_id.c
 

src/mainboard/intel/tglrvp/ec.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/ec.h>
+
+void mainboard_ec_init(void)
+{
+	const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}

src/mainboard/intel/tglrvp/mainboard.c

@@ -3,6 +3,7 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <device/device.h>
+#include <ec/ec.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <smbios.h>
@@ -24,6 +25,8 @@ static void mainboard_init(void *chip_info)
 
 	pads = variant_gpio_table(&num);
 	gpio_configure_pads(pads, num);
+
+	mainboard_ec_init();
 }
 
 static void mainboard_enable(struct device *dev)

src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h

@@ -41,6 +41,8 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
 
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
 /* Log EC wake events plus EC shutdown events */
 #define MAINBOARD_EC_LOG_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -256,7 +256,11 @@ chip soc/intel/tigerlake
 		device pci 1e.1 off end # UART1			0xA0A9
 		device pci 1e.2 off end # GSPI0			0xA0AA
 		device pci 1e.3 off end # GSPI1			0xA0AB
-		device pci 1f.0 on  end # eSPI			0xA080 - A09F
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # eSPI                                      0xA080 - A09F
 		device pci 1f.1 on  end # P2SB			0xA0A0
 		device pci 1f.2 hidden  # PMC			0xA0A1
 			# The pmc_mux chip driver is a placeholder for the

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -252,7 +252,11 @@ chip soc/intel/tigerlake
 		device pci 1e.1 off end # UART1			0xA0A9
 		device pci 1e.2 off end # GSPI0			0xA0AA
 		device pci 1e.3 off end # GSPI1			0xA0AB
-		device pci 1f.0 on  end # eSPI			0xA080 - A09F
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # eSPI                                      0xA080 - A09F
 		device pci 1f.1 on  end # P2SB			0xA0A0
 		device pci 1f.2 hidden  # PMC                   0xA0A1
 			# The pmc_mux chip driver is a placeholder for the