mb/starlabs/lite: Simplify the flash layout
Remove the sections that coreboot doesn't need to know about. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ide6c0d44f1f9ad9b962d2b8e14ac91e87f5ca031 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65453 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes
Martin Roth
parent
7710c68e2a
commit
d061c74949
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@ -1,88 +1,49 @@
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# Start End Length
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# Complete IFWI Map
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# Start (hex) End (hex) Length (hex) Area Name
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# ----------- --------- ------------ ---------
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#
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# 00000000 007FFFFF 00800000 Full Flash Image
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# 00000014 00000017 00000004 FLMAP0 - Flash Map 0 Register
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# 00000018 0000001B 00000004 FLMAP1 - Flash Map 1 Register
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# 0000001C 0000001F 00000004 FLMAP2 - Flash Map 2 Register
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# 00000030 0000003B 0000000C FCBA - Flash Component Registers
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# 00000040 00000043 00000004 FLREG0 - Flash Region 0 (Flash Descriptor) Register
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# 00000044 00000047 00000004 FLREG1 - Flash Region 1 (IFWI) Register
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# 00000048 0000004B 00000004 FLREG2 - Flash Region 2 (Intel(R) TXE) Register
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# 00000050 00000053 00000004 FLREG4 - Flash Region 4 (Platform Data) Register
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# 00000054 00000057 00000004 FLREG5 - Flash Region 5 (Device Expansion) Register
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# 00000060 00000063 00000004 FLREG8 - Flash Region 8 (Embedded Controller) Register
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# 00000080 00000083 00000004 FLMSTR1 - Flash Master 1 (Host CPU/BIOS)
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# 00000084 00000087 00000004 FLMSTR2 - Flash Master 2 (Intel(R) TXE)
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# 00000090 00000093 00000004 FLMSTR5 - Flash Master 5 (EC)
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# 00000100 000002FF 00000200 FPSBA - SoC Straps (Including Padding)
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# 00000DF0 00000EFF 00000110 VSCC Table
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# 00000DF0 00000DF7 00000008 GD25LQ64
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# 00001000 0037FFFF 0037F000 Boot Partition 1
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# 00001000 000C2FFF 000C2000 Primary Boot Partition
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# 00001200 0000120F 00000010 IFP Overrides Partition
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# 00001210 00001317 00000108 Unified Emulation Partition (UEP)
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# 00002000 00002FFF 00001000 OEM SMIP Partition
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# 00003000 0000DFFF 0000B000 CSE RBE Partition
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# 0000E000 0001CFFF 0000F000 PMCP
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# 0001D000 0007DFFF 00061000 CSE BUP Partition
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# 0007E000 000A3FFF 00026000 uCode Partition
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# 0007E040 0009083F 00012800 uCode Patch 1
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# 00090840 000A303F 00012800 uCode Patch 2
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# 000A4000 000C0FFF 0001D000 IBB Partition
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# 000C1000 000C2FFF 00002000 Debug Token Partition
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# 000C3000 001C6FFF 00104000 Secondary Boot Partition
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# 000C4000 001C6FFF 00103000 CSE Main Partition
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# 00380000 006FEFFF 0037F000 Boot Partition 2
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# 00380000 003801FF 00000200 Primary Boot Partition
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# 00380200 0062FFFF 002AFE00 Secondary Boot Partition
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# 00381000 0062FFFF 002AF000 OBB Partition
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# 006FF000 007FFFFF 00101000 TXE Data Region
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# coreboot only needs to know about the OBB. It's nested inside OBBP, to account for
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# the header.
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FLASH 8M {
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FLASH 8M {
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# 00000014 00000017 00000004 FLMAP0 - Flash Map 0 Register
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OBBP@0x382000 {
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FLMAP0@0x14 0x4
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# 00000018 0000001B 00000004 FLMAP1 - Flash Map 1 Register
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FLMAP1@0x18 0x4
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# 0000001C 0000001F 00000004 FLMAP2 - Flash Map 2 Register
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FLMAP2@0x1c 0x4
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# 00000030 0000003B 0000000C FCBA - Flash Component Registers
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FCBA@0x30 0xc
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# 00000040 00000043 00000004 FLREG0 - Flash Region 0 (Flash Descriptor) Register
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FLREG0@0x40 0x4
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# 00000044 00000047 00000004 FLREG1 - Flash Region 1 (IFWI) Register
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FLREG1@0x44 0x4
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# 00000048 0000004B 00000004 FLREG2 - Flash Region 2 (Intel(R) TXE) Register
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FLREG2@0x48 0x4
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# 00000050 00000053 00000004 FLREG4 - Flash Region 4 (Platform Data) Register
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FLREG4@0x50 0x4
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# 00000054 00000057 00000004 FLREG5 - Flash Region 5 (Device Expansion) Register
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FLREG5@0x54 0x4
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# 00000060 00000063 00000004 FLREG8 - Flash Region 8 (Embedded Controller) Register
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FLREG8@0x60 0x4
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# 00000080 00000083 00000004 FLMSTR1 - Flash Master 1 (Host CPU/BIOS)
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FLMSTR1@0x80 0x4
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# 00000084 00000087 00000004 FLMSTR2 - Flash Master 2 (Intel(R) TXE)
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FLMSTR2@0x84 0x4
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# 00000090 00000093 00000004 FLMSTR5 - Flash Master 5 (EC)
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FMSTR5@0x90 0x4
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# 00000100 000002FF 00000200 FPSBA - SoC Straps (Including Padding)
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FPSBA@0x100 0x200
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# 00000DF0 00000EFF 00000110 VSCC Table
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VSCC@0xdf0 0x110 {
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# 00000DF0 00000DF7 00000008 GD25LQ64
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VSCC3@0xdf 0x08
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}
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# APL and GLK will memory map the BIOS region. This will be mapped at (0x100000000 - sizeof(BIOS)).
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# BIOS = BP1 + BP2 = 0x6fe000.
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# 00001000 0037FFFF 0037F000 Boot Partition 1
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BP1@0x1000 0x37f000 {
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# 00001000 000ABFFF 000AB000 Primary Boot Partition
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PBP1@0x0 0xab000 {
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# 00001200 0000120F 00000010 IFP Overrides Partition
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IFPOP@0x200 0x10
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# 00001210 00001317 00000108 Unified Emulation Partition (UEP)
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UEP@0x210 0x108
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# 00002000 00002FFF 00001000 OEM SMIP Partition
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SMIP@0x1000 0x1000
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# 00003000 0000DFFF 0000B000 CSE RBE Partition
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CSERBE@0x2000 0xB000
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# 0000E000 0001CFFF 0000F000 PMCP
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PMCP@0xd000 0xf000
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# 0001D000 0007DFFF 00061000 CSE BUP Partition
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CSEBUP@0x1c000 0x61000
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# 0007E000 000A2FFF 00025000 uCode Partition
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UCODE@0x7d000 0x25000 {
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# 0007E040 0009043F 00012400 uCode Patch 1
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PATCH1@0x40 0x12400
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# 00090440 000A2C3F 00012800 uCode Patch 2
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PATCH2@0x12440 0x12800
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}
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# 000A3000 000A9FFF 00007000 IBB Partition
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IBB@0xa2000 0x7000
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# 000AA000 000ABFFF 00002000 Debug Token Partition
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DEBUG@0xa9000 0x2000
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}
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# 000AC000 001ADFFF 00102000 Secondary Boot Partition
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SBP1@0xac000 0x102000 {
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# 000AD000 001ADFFF 00101000 CSE Main Partition
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CSE@0x1000 0x101000
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}
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}
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# 00380000 006FEFFF 0037F000 Boot Partition 2
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BP2@0x380000 0x37f000 {
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# 00380000 003801FF 00000200 Primary Boot Partition
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PBP2@0x0 0x200
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# 00380200 00681FFF 00301E00 Secondary Boot Partition
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SBP2@0x200 0x301e00 {
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# 00381000 00681FFF 00301000 OBB Partition
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OBBP@0x1e00 0x2f8000 {
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OBB@0x0 0x2ae000 {
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OBB@0x0 0x2ae000 {
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FMAP@0xe000 0x10000
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FMAP@0xe000 0x10000
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COREBOOT(CBFS)@0x1e000 0x210000
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COREBOOT(CBFS)@0x1e000 0x210000
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@ -92,14 +53,7 @@ FLASH 8M {
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RW_MRC_CACHE@0x10000 0x10000
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RW_MRC_CACHE@0x10000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x10000
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RW_VAR_MRC_CACHE@0x20000 0x10000
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}
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}
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}
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SMMSTORE@0x26e000 0x40000
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NVSTORAGE@0x2ae000 0x48000 {
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SMMSTORE@0x0 0x40000
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}
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}
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}
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}
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}
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}
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# 006FF000 007FFFFF 00101000 TXE Data Region
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TXE@0x6ff000 0x101000
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}
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}
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