nb/intel/ironlake: Use DMIBAR/EPBAR macros
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ie0198a44589271de0335a51937e95662db891d98 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -1810,20 +1810,20 @@ static void setup_heci_uma(struct raminfo *info)
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pci_read_config32(NORTHBRIDGE, DMIBAR);
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pci_read_config32(NORTHBRIDGE, DMIBAR);
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if (info->memory_reserved_for_heci_mb) {
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if (info->memory_reserved_for_heci_mb) {
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write32(DEFAULT_DMIBAR + 0x14, read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
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DMIBAR32(0x14) &= ~0x80;
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write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80);
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write32(DEFAULT_RCBA + 0x14, read32(DEFAULT_RCBA + 0x14) & ~0x80);
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write32(DEFAULT_DMIBAR + 0x20, read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
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DMIBAR32(0x20) &= ~0x80;
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write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80);
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write32(DEFAULT_RCBA + 0x20, read32(DEFAULT_RCBA + 0x20) & ~0x80);
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write32(DEFAULT_DMIBAR + 0x2c, read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
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DMIBAR32(0x2c) &= ~0x80;
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write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80);
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write32(DEFAULT_RCBA + 0x30, read32(DEFAULT_RCBA + 0x30) & ~0x80);
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write32(DEFAULT_DMIBAR + 0x38, read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
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DMIBAR32(0x38) &= ~0x80;
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write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80);
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write32(DEFAULT_RCBA + 0x40, read32(DEFAULT_RCBA + 0x40) & ~0x80);
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write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
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write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
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write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK
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DMIBAR32(0x38) = 0x87000080; // OK
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while ((read16(DEFAULT_RCBA + 0x46) & 2) &&
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while ((read16(DEFAULT_RCBA + 0x46) & 2) &&
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read16(DEFAULT_DMIBAR + 0x3e) & 2)
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DMIBAR16(0x3e) & 2)
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;
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;
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}
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}
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@ -3604,12 +3604,12 @@ static void restore_274265(struct raminfo *info)
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static void dmi_setup(void)
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static void dmi_setup(void)
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{
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{
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gav(read8(DEFAULT_DMIBAR + 0x254));
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gav(DMIBAR8(0x254));
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write8(DEFAULT_DMIBAR + 0x254, 0x1);
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DMIBAR8(0x254) = 0x1;
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write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2);
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DMIBAR16(0x1b8) = 0x18f2;
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MCHBAR16_AND_OR(0x48, 0, 0x2);
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MCHBAR16_AND_OR(0x48, 0, 0x2);
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write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000);
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DMIBAR32(0xd68) |= 0x08000000;
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outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
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outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
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DEFAULT_GPIOBASE | 0x38);
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DEFAULT_GPIOBASE | 0x38);
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@ -4600,9 +4600,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
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}
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}
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u32 reg1c;
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u32 reg1c;
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pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
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pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
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reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
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reg1c = EPBAR32(0x01c); // = 0x8001 // OK
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pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
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pci_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
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write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
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EPBAR32(0x01c) = reg1c; // OK
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MCHBAR8(0xe08); // = 0x0
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MCHBAR8(0xe08); // = 0x0
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pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
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pci_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
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MCHBAR8_OR(0x1210, 2);
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MCHBAR8_OR(0x1210, 2);
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