intel/fsp_baytrail: Add PCI Root Port IRQ Routing
This change generates the ASL tables needed for the PCIe bridge routing. It generates this ASL (swizzled for each of the 8 functions) Name(RP1P, Package() { Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, }) Name(RP1A, Package() { Package() {0x0000ffff, 0, 0, 20 }, Package() {0x0000ffff, 1, 0, 21 }, Package() {0x0000ffff, 2, 0, 22 }, Package() {0x0000ffff, 3, 0, 23 }, }) Device(RP01) { Name(_ADR, 0x1c0001) Name(_PRW, Package() { 0, 0 }) Method(_PRT,0) { If(PICM) { Return (RP1A) } Else { Return (RP1P) } } } Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/8429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -40,22 +40,30 @@
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*IR1Eh SIO INT(ABCD) - PIRQ BDEF
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*IR1Fh LPC INT(ABCD) - PIRQ HGBC
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*/
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/* PCIe bridge routing */
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#define BRIDGE1_DEV PCIE_DEV
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/* PCI bridge IRQs need to be updated in both tables and need to match */
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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/*
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* Route each PIRQ[A-H] to a PIC IRQ[0-15]
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@ -41,22 +41,30 @@
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*IR1Eh SIO INT(ABCD) - PIRQ BDEF
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*IR1Fh LPC INT(ABCD) - PIRQ HGBC
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*/
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/* PCIe bridge routing */
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#define BRIDGE1_DEV PCIE_DEV
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/* PCI bridge IRQs need to be updated in both tables and need to match */
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H)
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C)
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/*
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* Route each PIRQ[A-H] to a PIC IRQ[0-15]
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@ -37,24 +37,89 @@
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#undef PIRQ_PIC_ROUTES
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#undef PIRQ_PIC
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#undef IRQROUTE_H
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#undef ROOTPORT_METHODS
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#undef RP_METHOD
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#undef ROOTPORT_IRQ_ROUTES
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#undef RP_IRQ_ROUTES
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#if defined(PIC_MODE)
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#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
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Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
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#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
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Name(prefix_ ## func_ ## P, Package() \
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{ \
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ACPI_DEV_IRQ(0x0000, 0, a_), \
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ACPI_DEV_IRQ(0x0000, 1, b_), \
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ACPI_DEV_IRQ(0x0000, 2, c_), \
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ACPI_DEV_IRQ(0x0000, 3, d_), \
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})
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/* define as blank so ROOTPORT_METHODS only gets inserted once */
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#define ROOTPORT_METHODS(prefix_, dev_)
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#else /* defined(PIC_MODE) */
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#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
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Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
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#endif
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#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
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Name(prefix_ ## func_ ## A, Package() \
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{ \
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ACPI_DEV_IRQ(0x0000, 0, a_), \
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ACPI_DEV_IRQ(0x0000, 1, b_), \
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ACPI_DEV_IRQ(0x0000, 2, c_), \
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ACPI_DEV_IRQ(0x0000, 3, d_), \
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})
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#define ROOTPORT_METHODS(prefix_, dev_) \
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RP_METHOD(prefix_, dev_, 0) \
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RP_METHOD(prefix_, dev_, 1) \
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RP_METHOD(prefix_, dev_, 2) \
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RP_METHOD(prefix_, dev_, 3) \
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RP_METHOD(prefix_, dev_, 4) \
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RP_METHOD(prefix_, dev_, 5) \
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RP_METHOD(prefix_, dev_, 6) \
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RP_METHOD(prefix_, dev_, 7)
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#endif /* defined(PIC_MODE) */
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#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
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ACPI_DEV_IRQ(dev_, 0, a_), \
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ACPI_DEV_IRQ(dev_, 1, b_), \
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ACPI_DEV_IRQ(dev_, 2, c_), \
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ACPI_DEV_IRQ(dev_, 3, d_)
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ACPI_DEV_IRQ(dev_, 3, d_), \
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#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
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ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
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ROOTPORT_METHODS(prefix_, dev_)
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#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
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RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
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RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
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RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
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RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
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RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
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RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
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#define RP_METHOD(prefix_, dev_, func_)\
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Device(prefix_ ## 0 ## func_) \
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{ \
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Name(_ADR, dev_ ## 000 ## func_) \
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Name(_PRW, Package() { \
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0, 0 \
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}) \
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Method(_PRT,0) { \
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If(PICM) { \
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Return (prefix_ ## func_ ## A) \
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} Else { \
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Return (prefix_ ## func_ ## P) \
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} \
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} \
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}
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/* Empty PIRQ_PIC definition. */
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#define PIRQ_PIC(pirq_, pic_irq_)
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@ -40,4 +40,11 @@ Method(_PRT)
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PCI_DEV_PIRQ_ROUTES
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})
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}
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}
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PCIE_BRIDGE_IRQ_ROUTES
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#undef PIC_MODE
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#include "irq_helper.h"
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PCIE_BRIDGE_IRQ_ROUTES
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@ -160,6 +160,9 @@ extern const struct baytrail_irq_route global_baytrail_irq_route;
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#define PIRQ_PIC(pirq_, pic_irq_) \
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[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
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/* used for ACPI only */
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#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_)
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#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
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#endif /* _BAYTRAIL_IRQ_H_ */
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