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mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry 

Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.

BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.

Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-10-08 17:04:10 -06:00 committed by Felix Held
parent e7f43502b5
commit d086e3d6e4
1 changed files with 28 additions and 0 deletions
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28
src/mainboard/google/guybrush/mainboard.c
View File

@ -13,11 +13,13 @@
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#define BACKLIGHT_GPIO GPIO_129 #define BACKLIGHT_GPIO GPIO_129
#define WWAN_AUX_RST_GPIO GPIO_18
#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN"
#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS"
#define METHOD_MAINBOARD_INI "\\_SB.MINI" #define METHOD_MAINBOARD_INI "\\_SB.MINI"
#define METHOD_MAINBOARD_WAK "\\_SB.MWAK" #define METHOD_MAINBOARD_WAK "\\_SB.MWAK"
#define METHOD_MAINBOARD_PTS "\\_SB.MPTS" #define METHOD_MAINBOARD_PTS "\\_SB.MPTS"
#define METHOD_MAINBOARD_S0X "\\_SB.MS0X"
/* /*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@ -151,6 +153,31 @@ static void mainboard_write_mpts(void)
acpigen_pop_len(); acpigen_pop_len();
} }
static void mainboard_assert_wwan_aux_reset(void)
{
if (variant_has_pcie_wwan())
acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO);
}
static void mainboard_deassert_wwan_aux_reset(void)
{
if (variant_has_pcie_wwan())
acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO);
}
static void mainboard_write_ms0x(void)
{
acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1);
/* S0ix Entry */
acpigen_write_if_lequal_op_int(ARG0_OP, 1);
mainboard_assert_wwan_aux_reset();
/* S0ix Exit */
acpigen_write_else();
mainboard_deassert_wwan_aux_reset();
acpigen_pop_len();
acpigen_pop_len();
}
static void mainboard_fill_ssdt(const struct device *dev) static void mainboard_fill_ssdt(const struct device *dev)
{ {
mainboard_write_blken(); mainboard_write_blken();
@ -158,6 +185,7 @@ static void mainboard_fill_ssdt(const struct device *dev)
mainboard_write_mini(); mainboard_write_mini();
mainboard_write_mpts(); mainboard_write_mpts();
mainboard_write_mwak(); mainboard_write_mwak();
mainboard_write_ms0x();
} }
static void mainboard_enable(struct device *dev) static void mainboard_enable(struct device *dev)