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Add support for Asus M4A785-M. 

Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Juhana Helovuo 2010-09-13 14:51:26 +00:00 committed by Myles Watson
parent 6c029e6963
commit d09d1f7846
24 changed files with 5470 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/asus/Kconfig
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@ -27,6 +27,8 @@ config BOARD_ASUS_A8V_E_SE
bool "A8V-E SE"
config BOARD_ASUS_M2V_MX_SE
bool "M2V-MX SE"
config BOARD_ASUS_M4A785M
bool "M4A785-M"
config BOARD_ASUS_MEW_AM
bool "MEW-AM"
config BOARD_ASUS_MEW_VM
@ -49,6 +51,7 @@ endchoice
source "src/mainboard/asus/a8n_e/Kconfig"
source "src/mainboard/asus/a8v-e_se/Kconfig"
source "src/mainboard/asus/m2v-mx_se/Kconfig"
source "src/mainboard/asus/m4a785-m/Kconfig"
source "src/mainboard/asus/mew-am/Kconfig"
source "src/mainboard/asus/mew-vm/Kconfig"
source "src/mainboard/asus/p2b/Kconfig"

110
src/mainboard/asus/m4a785-m/Kconfig Normal file
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@ -0,0 +1,110 @@
if BOARD_ASUS_M4A785M
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
select CPU_AMD_SOCKET_AM3
select DIMM_DDR2
select NORTHBRIDGE_AMD_AMDFAM10
select SOUTHBRIDGE_AMD_RS780
select SOUTHBRIDGE_AMD_SB700
select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
select SUPERIO_ITE_IT8712F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select CACHE_AS_RAM
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select GENERATE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select ENABLE_APIC_EXT_ID
select TINY_BOOTBLOCK
select GFXUMA
config MAINBOARD_DIR
string
default asus/m4a785-m
config APIC_ID_OFFSET
hex
default 0x0
config MAINBOARD_PART_NUMBER
string
default "M4A785-M"
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MAX_CPUS
int
default 8
config MAX_PHYSICAL_CPUS
int
default 2
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config MEM_TRAIN_SEQ
int
default 2
config SB_HT_CHAIN_ON_BUS0
int
default 1
config HT_CHAIN_END_UNITID_BASE
hex
default 0x1
config HT_CHAIN_UNITID_BASE
hex
default 0x0
config IRQ_SLOT_COUNT
int
default 19
config AMD_UCODE_PATCH_FILE
string
default "mc_patch_010000b6.h"
config RAMTOP
hex
default 0x2000000
config HEAP_SIZE
hex
default 0xc0000
config ACPI_SSDTX_NUM
int
default 0
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x83a2
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1043
config RAMBASE
hex
default 0x200000
config COMPRESS
hex
default 0
endif

75
src/mainboard/asus/m4a785-m/acpi/cpstate.asl Normal file
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@ -0,0 +1,75 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* This file defines the processor and performance state capability
* for each core in the system. It is included into the DSDT for each
* core. It assumes that each core of the system has the same performance
* characteristics.
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
{
Scope (\_PR) {
Processor(CPU0,0,0x808,0x06) {
#include "cpstate.asl"
}
Processor(CPU1,1,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU2,2,0x0,0x0) {
#include "cpstate.asl"
}
Processor(CPU3,3,0x0,0x0) {
#include "cpstate.asl"
}
}
*/
/* P-state support: The maximum number of P-states supported by the */
/* CPUs we'll use is 6. */
/* Get from AMI BIOS. */
Name(_PSS, Package(){
Package ()
{
0x00000AF0,
0x0000BF81,
0x00000002,
0x00000002,
0x00000000,
0x00000000
},
Package ()
{
0x00000578,
0x000076F2,
0x00000002,
0x00000002,
0x00000001,
0x00000001
}
})
Name(_PCT, Package(){
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
})
Method(_PPC, 0){
Return(0)
}

198
src/mainboard/asus/m4a785-m/acpi/debug.asl Normal file
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@ -0,0 +1,198 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
DefinitionBlock (
"DSDT.AML",
"DSDT",
0x01,
"XXXXXX",
"XXXXXXXX",
0x00010001
)
{
#include "debug.asl"
}
*/
/*
* 0x80: POST_BASE
* 0x3F8: DEBCOM_BASE
* X80: POST_REGION
* P80: PORT80
*
* CREG: DEBCOM_REGION
* CUAR: DEBCOM_UART
* CDAT: DEBCOM_DATA
* CDLM: DEBCOM_DLM
* DLCR: DEBCOM_LCR
* CMCR: DEBCOM_MCR
* CLSR: DEBCOM_LSR
*
* DEBUG_INIT DINI
*/
OperationRegion(X80, SystemIO, 0x80, 1)
Field(X80, ByteAcc, NoLock, Preserve)
{
P80, 8
}
OperationRegion(CREG, SystemIO, 0x3F8, 8)
Field(CREG, ByteAcc, NoLock, Preserve)
{
CDAT, 8,
CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8
}
/*
* DINI
* Initialize the COM port to 115,200 8-N-1
*/
Method(DINI)
{
store(0x83, DLCR)
store(0x01, CDAT) /* 115200 baud (low) */
store(0x00, CDLM) /* 115200 baud (high) */
store(0x03, DLCR) /* word=8 stop=1 parity=none */
store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */
store(0x00, CDLM) /* turn off interrupts */
}
/*
* THRE
* Wait for COM port transmitter holding register to go empty
*/
Method(THRE)
{
and(CLSR, 0x20, local0)
while (Lequal(local0, Zero)) {
and(CLSR, 0x20, local0)
}
}
/*
* OUTX
* Send a single raw character
*/
Method(OUTX, 1)
{
THRE()
store(Arg0, CDAT)
}
/*
* OUTC
* Send a single character, expanding LF into CR/LF
*/
Method(OUTC, 1)
{
if (LEqual(Arg0, 0x0a)) {
OUTX(0x0d)
}
OUTX(Arg0)
}
/*
* DBGN
* Send a single hex nibble
*/
Method(DBGN, 1)
{
and(Arg0, 0x0f, Local0)
if (LLess(Local0, 10)) {
add(Local0, 0x30, Local0)
} else {
add(Local0, 0x37, Local0)
}
OUTC(Local0)
}
/*
* DBGB
* Send a hex byte
*/
Method(DBGB, 1)
{
ShiftRight(Arg0, 4, Local0)
DBGN(Local0)
DBGN(Arg0)
}
/*
* DBGW
* Send a hex word
*/
Method(DBGW, 1)
{
ShiftRight(Arg0, 8, Local0)
DBGB(Local0)
DBGB(Arg0)
}
/*
* DBGD
* Send a hex Dword
*/
Method(DBGD, 1)
{
ShiftRight(Arg0, 16, Local0)
DBGW(Local0)
DBGW(Arg0)
}
/*
* DBGO
* Send either a string or an integer
*/
Method(DBGO, 1)
{
/* DINI() */
if (LEqual(ObjectType(Arg0), 1)) {
if (LGreater(Arg0, 0xffff)) {
DBGD(Arg0)
} else {
if (LGreater(Arg0, 0xff)) {
DBGW(Arg0)
} else {
DBGB(Arg0)
}
}
} else {
Name(BDBG, Buffer(80) {})
store(Arg0, BDBG)
store(0, Local1)
while (One) {
store(GETC(BDBG, Local1), Local0)
if (LEqual(Local0, 0)) {
return (0)
}
OUTC(Local0)
Increment(Local1)
}
}
return (0)
}
/* Get a char from a string */
Method(GETC, 2)
{
CreateByteField(Arg0, Arg1, DBGC)
return (DBGC)
}

118
src/mainboard/asus/m4a785-m/acpi/globutil.asl Normal file
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@ -0,0 +1,118 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
Scope(\_SB) {
#include "globutil.asl"
}
*/
/* string compare functions */
Method(MIN, 2)
{
if (LLess(Arg0, Arg1)) {
Return(Arg0)
} else {
Return(Arg1)
}
}
Method(SLEN, 1)
{
Store(Arg0, Local0)
Return(Sizeof(Local0))
}
Method(S2BF, 1)
{
Add(SLEN(Arg0), One, Local0)
Name(BUFF, Buffer(Local0) {})
Store(Arg0, BUFF)
Return(BUFF)
}
/* Strong string compare. Checks both length and content */
Method(SCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
Store(Zero, Local4)
Store(SLEN(Arg0), Local5)
Store(SLEN(Arg1), Local6)
Store(MIN(Local5, Local6), Local7)
While(LLess(Local4, Local7)) {
Store(Derefof(Index(Local0, Local4)), Local2)
Store(Derefof(Index(Local1, Local4)), Local3)
if (LGreater(Local2, Local3)) {
Return(One)
} else {
if (LLess(Local2, Local3)) {
Return(Ones)
}
}
Increment(Local4)
}
if (LLess(Local4, Local5)) {
Return(One)
} else {
if (LLess(Local4, Local6)) {
Return(Ones)
} else {
Return(Zero)
}
}
}
/* Weak string compare. Checks to find Arg1 at beginning of Arg0.
* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on
* Pass.
*/
Method(WCMP, 2)
{
Store(S2BF(Arg0), Local0)
Store(S2BF(Arg1), Local1)
if (LLess(SLEN(Arg0), SLEN(Arg1))) {
Return(0)
}
Store(Zero, Local2)
Store(SLEN(Arg1), Local3)
While(LLess(Local2, Local3)) {
if (LNotEqual(Derefof(Index(Local0, Local2)),
Derefof(Index(Local1, Local2)))) {
Return(0)
}
Increment(Local2)
}
Return(One)
}
/* ARG0 = IRQ Number(0-15)
* Returns Bit Map
*/
Method(I2BM, 1)
{
Store(0, Local0)
if (LNotEqual(ARG0, 0)) {
Store(1, Local1)
ShiftLeft(Local1, ARG0, Local0)
}
Return(Local0)
}

244
src/mainboard/asus/m4a785-m/acpi/ide.asl Normal file
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@ -0,0 +1,244 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
Scope (_SB) {
Device(PCI0) {
Device(IDEC) {
Name(_ADR, 0x00140001)
#include "ide.asl"
}
}
}
*/
/* Some timing tables */
Name(UDTT, Package(){ /* Udma timing table */
120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
})
Name(MDTT, Package(){ /* MWDma timing table */
480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
})
Name(POTT, Package(){ /* Pio timing table */
600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
})
/* Some timing register value tables */
Name(MDRT, Package(){ /* MWDma timing register table */
0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
})
Name(PORT, Package(){
0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
})
OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
Field(ICRG, AnyAcc, NoLock, Preserve)
{
PPTS, 8, /* Primary PIO Slave Timing */
PPTM, 8, /* Primary PIO Master Timing */
OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
PMTM, 8, /* Primary MWDMA Master Timing */
OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
PPSM, 4, /* Primary PIO slave Mode */
OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
PDSM, 4, /* Primary UltraDMA Mode */
}
Method(GTTM, 1) /* get total time*/
{
Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
Increment(Local0)
Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
Increment(Local1)
Return(Multiply(30, Add(Local0, Local1)))
}
Device(PRID)
{
Name (_ADR, Zero)
Method(_GTM, 0)
{
NAME(OTBF, Buffer(20) { /* out buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
/* Just return if the channel is disabled */
If(And(PPCR, 0x01)) { /* primary PIO control */
Return(OTBF)
}
/* Always tell them independent timing available and IOChannelReady used on both drives */
Or(BFFG, 0x1A, BFFG)
Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
If(And(PDCR, 0x01)) { /* It's under UDMA mode */
Or(BFFG, 0x01, BFFG)
Store(DerefOf(Index(UDTT, PDMM)), DSD0)
}
Else {
Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
}
If(And(PDCR, 0x02)) { /* It's under UDMA mode */
Or(BFFG, 0x04, BFFG)
Store(DerefOf(Index(UDTT, PDSM)), DSD1)
}
Else {
Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
}
Return(OTBF) /* out buffer */
} /* End Method(_GTM) */
Method(_STM, 3, NotSerialized)
{
NAME(INBF, Buffer(20) { /* in buffer */
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
})
CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
CreateDwordField(INBF, 16, BFFG) /*buffer flag */
Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
Divide(Local0, 7, PDMM,)
Or(PDCR, 0x01, PDCR)
}
Else {
If(LNotEqual(DSD0, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTM)
}
}
If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
Divide(Local0, 7, PDSM,)
Or(PDCR, 0x02, PDCR)
}
Else {
If(LNotEqual(DSD1, 0xFFFFFFFF)) {
Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
Store(DerefOf(Index(MDRT, Local0)), PMTS)
}
}
/* Return(INBF) */
} /*End Method(_STM) */
Device(MST)
{
Name(_ADR, 0)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xA0, CMDA)
Store(0xA0, CMDB)
Store(0xA0, CMDC)
Or(PPMM, 0x08, POMD)
If(And(PDCR, 0x01)) {
Or(PDMM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTM),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(MST) */
Device(SLAV)
{
Name(_ADR, 1)
Method(_GTF) {
Name(CMBF, Buffer(21) {
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
})
CreateByteField(CMBF, 1, POMD)
CreateByteField(CMBF, 8, DMMD)
CreateByteField(CMBF, 5, CMDA)
CreateByteField(CMBF, 12, CMDB)
CreateByteField(CMBF, 19, CMDC)
Store(0xB0, CMDA)
Store(0xB0, CMDB)
Store(0xB0, CMDC)
Or(PPSM, 0x08, POMD)
If(And(PDCR, 0x02)) {
Or(PDSM, 0x40, DMMD)
}
Else {
Store(Match
(MDTT, MLE, GTTM(PMTS),
MTR, 0, 0), Local0)
If(LLess(Local0, 3)) {
Or(0x20, Local0, DMMD)
}
}
Return(CMBF)
}
} /* End Device(SLAV) */
}

300
src/mainboard/asus/m4a785-m/acpi/routing.asl Normal file
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@ -0,0 +1,300 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "routing.asl"
}
*/
/* Routing is in System Bus scope */
Scope(\_SB) {
Name(PR0, Package(){
/* NB devices */
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, INTA, 0 },
Package(){0x0004FFFF, 1, INTB, 0 },
Package(){0x0004FFFF, 2, INTC, 0 },
Package(){0x0004FFFF, 3, INTD, 0 },
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Package(){0x0005FFFF, 0, INTB, 0 }, */
/* Package(){0x0005FFFF, 1, INTC, 0 }, */
/* Package(){0x0005FFFF, 2, INTD, 0 }, */
/* Package(){0x0005FFFF, 3, INTA, 0 }, */
/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
Package(){0x0006FFFF, 0, INTC, 0 },
Package(){0x0006FFFF, 1, INTD, 0 },
Package(){0x0006FFFF, 2, INTA, 0 },
Package(){0x0006FFFF, 3, INTB, 0 },
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
Package(){0x0007FFFF, 0, INTD, 0 },
Package(){0x0007FFFF, 1, INTA, 0 },
Package(){0x0007FFFF, 2, INTB, 0 },
Package(){0x0007FFFF, 3, INTC, 0 },
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */
/* Bus 0, Dev 17 - SATA controller #2 */
/* Bus 0, Dev 18 - SATA controller #1 */
Package(){0x0011FFFF, 1, INTA, 0 },
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0012FFFF, 0, INTA, 0 },
Package(){0x0012FFFF, 1, INTB, 0 },
Package(){0x0013FFFF, 0, INTA, 0 },
Package(){0x0013FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTA, 0 },
/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
Package(){0x0014FFFF, 0, INTA, 0 },
Package(){0x0014FFFF, 1, INTB, 0 },
Package(){0x0014FFFF, 2, INTC, 0 },
Package(){0x0014FFFF, 3, INTD, 0 },
})
Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Package(){0x0001FFFF, 0, 0, 18 }, */
/* package(){0x0001FFFF, 1, 0, 19 }, */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
Package(){0x0002FFFF, 0, 0, 18 },
/* Package(){0x0002FFFF, 1, 0, 19 }, */
/* Package(){0x0002FFFF, 2, 0, 16 }, */
/* Package(){0x0002FFFF, 3, 0, 17 }, */
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
Package(){0x0003FFFF, 0, 0, 19 },
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
Package(){0x0004FFFF, 0, 0, 16 },
/* Package(){0x0004FFFF, 1, 0, 17 }, */
/* Package(){0x0004FFFF, 2, 0, 18 }, */
/* Package(){0x0004FFFF, 3, 0, 19 }, */
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
/* Package(){0x0005FFFF, 0, 0, 17 }, */
/* Package(){0x0005FFFF, 1, 0, 18 }, */
/* Package(){0x0005FFFF, 2, 0, 19 }, */
/* Package(){0x0005FFFF, 3, 0, 16 }, */
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
/* Package(){0x0006FFFF, 0, 0, 18 }, */
/* Package(){0x0006FFFF, 1, 0, 19 }, */
/* Package(){0x0006FFFF, 2, 0, 16 }, */
/* Package(){0x0006FFFF, 3, 0, 17 }, */
/* Bus 0, Dev 7 - PCIe Bridge for network card */
/* Package(){0x0007FFFF, 0, 0, 19 }, */
/* Package(){0x0007FFFF, 1, 0, 16 }, */
/* Package(){0x0007FFFF, 2, 0, 17 }, */
/* Package(){0x0007FFFF, 3, 0, 18 }, */
/* Bus 0, Dev 9 - PCIe Bridge for network card */
Package(){0x0009FFFF, 0, 0, 17 },
/* Package(){0x0009FFFF, 1, 0, 16 }, */
/* Package(){0x0009FFFF, 2, 0, 17 }, */
/* Package(){0x0009FFFF, 3, 0, 18 }, */
/* Bus 0, Dev A - PCIe Bridge for network card */
Package(){0x000AFFFF, 0, 0, 18 },
/* Package(){0x000AFFFF, 1, 0, 16 }, */
/* Package(){0x000AFFFF, 2, 0, 17 }, */
/* Package(){0x000AFFFF, 3, 0, 18 }, */
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices in APIC mode */
/* Bus 0, Dev 17 - SATA controller #2 */
/* Bus 0, Dev 18 - SATA controller #1 */
Package(){0x0011FFFF, 0, 0, 22 },
/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
Package(){0x0012FFFF, 0, 0, 16 },
Package(){0x0012FFFF, 1, 0, 17 },
Package(){0x0013FFFF, 0, 0, 18 },
Package(){0x0013FFFF, 1, 0, 19 },
Package(){0x0014FFFF, 0, 0, 16 },
/* Package(){0x00130004, 2, 0, 18 }, */
/* Package(){0x00130005, 3, 0, 19 }, */
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
/* Package(){0x00140004, 2, 0, 18 }, */
/* Package(){0x00140004, 3, 0, 19 }, */
/* Package(){0x00140005, 1, 0, 17 }, */
/* Package(){0x00140006, 1, 0, 17 }, */
})
Name(PR1, Package(){
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, INTA, 0 },
Package(){0x0005FFFF, 1, INTB, 0 },
Package(){0x0005FFFF, 2, INTC, 0 },
Package(){0x0005FFFF, 3, INTD, 0 },
})
Name(APR1, Package(){
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
Package(){0x0005FFFF, 0, 0, 18 },
Package(){0x0005FFFF, 1, 0, 19 },
/* Package(){0x0005FFFF, 2, 0, 20 }, */
/* Package(){0x0005FFFF, 3, 0, 17 }, */
})
Name(PS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS2, Package(){
/* The external GFX - Hooked to PCIe slot 2 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, INTA, 0 },
Package(){0x0000FFFF, 1, INTB, 0 },
Package(){0x0000FFFF, 2, INTC, 0 },
Package(){0x0000FFFF, 3, INTD, 0 },
})
Name(APS4, Package(){
/* PCIe slot - Hooked to PCIe slot 4 */
Package(){0x0000FFFF, 0, 0, 16 },
Package(){0x0000FFFF, 1, 0, 17 },
Package(){0x0000FFFF, 2, 0, 18 },
Package(){0x0000FFFF, 3, 0, 19 },
})
Name(PS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, INTB, 0 },
Package(){0x0000FFFF, 1, INTC, 0 },
Package(){0x0000FFFF, 2, INTD, 0 },
Package(){0x0000FFFF, 3, INTA, 0 },
})
Name(APS5, Package(){
/* PCIe slot - Hooked to PCIe slot 5 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, INTC, 0 },
Package(){0x0000FFFF, 1, INTD, 0 },
Package(){0x0000FFFF, 2, INTA, 0 },
Package(){0x0000FFFF, 3, INTB, 0 },
})
Name(APS6, Package(){
/* PCIe slot - Hooked to PCIe slot 6 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS7, Package(){
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
Package(){0x0000FFFF, 0, 0, 19 },
Package(){0x0000FFFF, 1, 0, 16 },
Package(){0x0000FFFF, 2, 0, 17 },
Package(){0x0000FFFF, 3, 0, 18 },
})
Name(PS9, Package(){
/* PCIe slot - Hooked to PCIe slot 9 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APS9, Package(){
/* PCIe slot - Hooked to PCIe slot 9 */
Package(){0x0000FFFF, 0, 0, 17 },
Package(){0x0000FFFF, 1, 0, 18 },
Package(){0x0000FFFF, 2, 0, 19 },
Package(){0x0000FFFF, 3, 0, 16 },
})
Name(PSa, Package(){
/* PCIe slot - Hooked to PCIe slot 10 */
Package(){0x0000FFFF, 0, INTD, 0 },
Package(){0x0000FFFF, 1, INTA, 0 },
Package(){0x0000FFFF, 2, INTB, 0 },
Package(){0x0000FFFF, 3, INTC, 0 },
})
Name(APSa, Package(){
/* PCIe slot - Hooked to PCIe slot 10 */
Package(){0x0000FFFF, 0, 0, 18 },
Package(){0x0000FFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
Name(PCIB, Package(){
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
Package(){0x0005FFFF, 0, 0, 0x14 },
Package(){0x0005FFFF, 1, 0, 0x15 },
Package(){0x0005FFFF, 2, 0, 0x16 },
Package(){0x0005FFFF, 3, 0, 0x17 },
Package(){0x0006FFFF, 0, 0, 0x15 },
Package(){0x0006FFFF, 1, 0, 0x16 },
Package(){0x0006FFFF, 2, 0, 0x17 },
Package(){0x0006FFFF, 3, 0, 0x14 },
Package(){0x0007FFFF, 0, 0, 0x16 },
Package(){0x0007FFFF, 1, 0, 0x17 },
Package(){0x0007FFFF, 2, 0, 0x14 },
Package(){0x0007FFFF, 3, 0, 0x15 },
})
}

149
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* simple name description */
/*
Scope (_SB) {
Device(PCI0) {
Device(SATA) {
Name(_ADR, 0x00110000)
#include "sata.asl"
}
}
}
*/
Name(STTM, Buffer(20) {
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
0x1f, 0x00, 0x00, 0x00
})
/* Start by clearing the PhyRdyChg bits */
Method(_INI) {
\_GPE._L1F()
}
Device(PMRY)
{
Name(_ADR, 0)
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(PMST) {
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P0IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
}/* end of PMST */
Device(PSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P1IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of PSLA */
} /* end of PMRY */
Device(SEDY)
{
Name(_ADR, 1) /* IDE Scondary Channel */
Method(_GTM, 0x0, NotSerialized) {
Return(STTM)
}
Method(_STM, 0x3, NotSerialized) {}
Device(SMST)
{
Name(_ADR, 0)
Method(_STA,0) {
if (LGreater(P2IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SMST */
Device(SSLA)
{
Name(_ADR, 1)
Method(_STA,0) {
if (LGreater(P3IS,0)) {
return (0x0F) /* sata is visible */
}
else {
return (0x00) /* sata is missing */
}
}
} /* end of SSLA */
} /* end of SEDY */
/* SATA Hot Plug Support */
Scope(\_GPE) {
Method(_L1F,0x0,NotSerialized) {
if (\_SB.P0PR) {
if (LGreater(\_SB.P0IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P0PR)
}
if (\_SB.P1PR) {
if (LGreater(\_SB.P1IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P1PR)
}
if (\_SB.P2PR) {
if (LGreater(\_SB.P2IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P2PR)
}
if (\_SB.P3PR) {
if (LGreater(\_SB.P3IS,0)) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
store(one, \_SB.P3PR)
}
}
}

93
src/mainboard/asus/m4a785-m/acpi/statdef.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Status and notification definitions */
#define STA_MISSING 0x00
#define STA_PRESENT 0x01
#define STA_ENABLED 0x03
#define STA_DISABLED 0x09
#define STA_INVISIBLE 0x0B
#define STA_UNAVAILABLE 0x0D
#define STA_VISIBLE 0x0F
/* SMBus status codes */
#define SMB_OK 0x00
#define SMB_UnknownFail 0x07
#define SMB_DevAddrNAK 0x10
#define SMB_DeviceError 0x11
#define SMB_DevCmdDenied 0x12
#define SMB_UnknownErr 0x13
#define SMB_DevAccDenied 0x17
#define SMB_Timeout 0x18
#define SMB_HstUnsuppProtocol 0x19
#define SMB_Busy 0x1A
#define SMB_PktChkError 0x1F
/* Device Object Notification Values */
#define NOTIFY_BUS_CHECK 0x00
#define NOTIFY_DEVICE_CHECK 0x01
#define NOTIFY_DEVICE_WAKE 0x02
#define NOTIFY_EJECT_REQUEST 0x03
#define NOTIFY_DEVICE_CHECK_JR 0x04
#define NOTIFY_FREQUENCY_ERROR 0x05
#define NOTIFY_BUS_MODE 0x06
#define NOTIFY_POWER_FAULT 0x07
#define NOTIFY_CAPABILITIES 0x08
#define NOTIFY_PLD_CHECK 0x09
#define NOTIFY_SLIT_UPDATE 0x0B
/* Battery Device Notification Values */
#define NOTIFY_BAT_STATUSCHG 0x80
#define NOTIFY_BAT_INFOCHG 0x81
#define NOTIFY_BAT_MAINTDATA 0x82
/* Power Source Object Notification Values */
#define NOTIFY_PWR_STATUSCHG 0x80
/* Thermal Zone Object Notification Values */
#define NOTIFY_TZ_STATUSCHG 0x80
#define NOTIFY_TZ_TRIPPTCHG 0x81
#define NOTIFY_TZ_DEVLISTCHG 0x82
#define NOTIFY_TZ_RELTBLCHG 0x83
/* Power Button Notification Values */
#define NOTIFY_POWER_BUTTON 0x80
/* Sleep Button Notification Values */
#define NOTIFY_SLEEP_BUTTON 0x80
/* Lid Notification Values */
#define NOTIFY_LID_STATUSCHG 0x80
/* Processor Device Notification Values */
#define NOTIFY_CPU_PPCCHG 0x80
#define NOTIFY_CPU_CSTATECHG 0x81
#define NOTIFY_CPU_THROTLCHG 0x82
/* User Presence Device Notification Values */
#define NOTIFY_USR_PRESNCECHG 0x80
/* Battery Device Notification Values */
#define NOTIFY_ALS_ILLUMCHG 0x80
#define NOTIFY_ALS_COLORTMPCHG 0x81
#define NOTIFY_ALS_RESPCHG 0x82

161
src/mainboard/asus/m4a785-m/acpi/usb.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* simple name description */
/*
DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
)
{
#include "usb.asl"
}
*/
Method(UCOC, 0) {
Sleep(20)
Store(0x13,CMTI)
Store(0,GPSL)
}
/* USB Port 0 overcurrent uses Gpm 0 */
If(LLessEqual(UOM0,9)) {
Scope (\_GPE) {
Method (_L13) {
UCOC()
if(LEqual(GPB0,PLC0)) {
Not(PLC0,PLC0)
Store(PLC0, \_SB.PT0D)
}
}
}
}
/* USB Port 1 overcurrent uses Gpm 1 */
If (LLessEqual(UOM1,9)) {
Scope (\_GPE) {
Method (_L14) {
UCOC()
if (LEqual(GPB1,PLC1)) {
Not(PLC1,PLC1)
Store(PLC1, \_SB.PT1D)
}
}
}
}
/* USB Port 2 overcurrent uses Gpm 2 */
If (LLessEqual(UOM2,9)) {
Scope (\_GPE) {
Method (_L15) {
UCOC()
if (LEqual(GPB2,PLC2)) {
Not(PLC2,PLC2)
Store(PLC2, \_SB.PT2D)
}
}
}
}
/* USB Port 3 overcurrent uses Gpm 3 */
If (LLessEqual(UOM3,9)) {
Scope (\_GPE) {
Method (_L16) {
UCOC()
if (LEqual(GPB3,PLC3)) {
Not(PLC3,PLC3)
Store(PLC3, \_SB.PT3D)
}
}
}
}
/* USB Port 4 overcurrent uses Gpm 4 */
If (LLessEqual(UOM4,9)) {
Scope (\_GPE) {
Method (_L19) {
UCOC()
if (LEqual(GPB4,PLC4)) {
Not(PLC4,PLC4)
Store(PLC4, \_SB.PT4D)
}
}
}
}
/* USB Port 5 overcurrent uses Gpm 5 */
If (LLessEqual(UOM5,9)) {
Scope (\_GPE) {
Method (_L1A) {
UCOC()
if (LEqual(GPB5,PLC5)) {
Not(PLC5,PLC5)
Store(PLC5, \_SB.PT5D)
}
}
}
}
/* USB Port 6 overcurrent uses Gpm 6 */
If (LLessEqual(UOM6,9)) {
Scope (\_GPE) {
/* Method (_L1C) { */
Method (_L06) {
UCOC()
if (LEqual(GPB6,PLC6)) {
Not(PLC6,PLC6)
Store(PLC6, \_SB.PT6D)
}
}
}
}
/* USB Port 7 overcurrent uses Gpm 7 */
If (LLessEqual(UOM7,9)) {
Scope (\_GPE) {
/* Method (_L1D) { */
Method (_L07) {
UCOC()
if (LEqual(GPB7,PLC7)) {
Not(PLC7,PLC7)
Store(PLC7, \_SB.PT7D)
}
}
}
}
/* USB Port 8 overcurrent uses Gpm 8 */
If (LLessEqual(UOM8,9)) {
Scope (\_GPE) {
Method (_L17) {
if (LEqual(G8IS,PLC8)) {
Not(PLC8,PLC8)
Store(PLC8, \_SB.PT8D)
}
}
}
}
/* USB Port 9 overcurrent uses Gpm 9 */
If (LLessEqual(UOM9,9)) {
Scope (\_GPE) {
Method (_L0E) {
if (LEqual(G9IS,0)) {
Store(1,\_SB.PT9D)
}
}
}
}

273
src/mainboard/asus/m4a785-m/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include "mb_sysconf.h"
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
static void dump_mem(u32 start, u32 end)
{
u32 i;
print_debug("dump_mem:");
for (i = start; i < end; i++) {
if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
print_debug("\n");
}
#endif
extern const unsigned char AmlCode[];
extern const unsigned char AmlCode_ssdt[];
#if CONFIG_ACPI_SSDTX_NUM >= 1
extern const unsigned char AmlCode_ssdt2[];
extern const unsigned char AmlCode_ssdt3[];
extern const unsigned char AmlCode_ssdt4[];
extern const unsigned char AmlCode_ssdt5[];
#endif
#define IO_APIC_ADDR 0xfec00000UL
unsigned long acpi_fill_mcfg(unsigned long current)
{
/* Just a dummy */
return current;
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
/* Write SB700 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, 0xF);
/* 0: mean bus 0--->ISA */
/* 0: PIC 0 */
/* 2: APIC 2 */
/* 5 mean: 0101 --> Edige-triggered, Active high */
/* create all subtables for processors */
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
/* 1: LINT1 connect to NMI */
return current;
}
unsigned long write_acpi_tables(unsigned long start)
{
unsigned long current;
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
acpi_header_t *dsdt;
acpi_header_t *ssdt;
#if CONFIG_ACPI_SSDTX_NUM >= 1
acpi_header_t *ssdtx;
void *p;
int i;
#endif
get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
/* Align ACPI tables to 16 bytes */
start = (start + 0x0f) & -0x10;
current = start;
printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
rsdp = (acpi_rsdp_t *) current;
current += sizeof(acpi_rsdp_t);
rsdt = (acpi_rsdt_t *) current;
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, NULL);
acpi_write_rsdt(rsdt);
/*
* We explicitly add these tables later on:
*/
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current);
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
acpi_add_table(rsdp, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current);
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
current += madt->header.length;
acpi_add_table(rsdp, madt);
/* SRAT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
srat = (acpi_srat_t *) current;
acpi_create_srat(srat);
current += srat->header.length;
acpi_add_table(rsdp, srat);
/* SLIT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
slit = (acpi_slit_t *) current;
acpi_create_slit(slit);
current += slit->header.length;
acpi_add_table(rsdp, slit);
/* SSDT */
current = ( current + 0x0f) & -0x10;
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
ssdt = (acpi_header_t *)current;
memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
current += ssdt->length;
memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
update_ssdt((void*)ssdt);
/* recalculate checksum */
ssdt->checksum = 0;
ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
acpi_add_table(rsdp,ssdt);
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
current = acpi_add_ssdt_pstates(rsdp, current);
#if CONFIG_ACPI_SSDTX_NUM >= 1
/* same htio, but different position? We may have to copy,
change HCIN, and recalculate the checknum and add_table */
for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
if((sysconf.pci1234[i] & 1) != 1 ) continue;
u8 c;
if (i < 7) {
c = (u8) ('4' + i - 1);
} else {
c = (u8) ('A' + i - 1 - 6);
}
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
ssdtx = (acpi_header_t *)current;
switch (sysconf.hcid[i]) {
case 1:
p = &AmlCode_ssdt2;
break;
case 2:
p = &AmlCode_ssdt3;
break;
case 3: /* 8131 */
p = &AmlCode_ssdt4;
break;
default:
/* HTX no io apic */
p = &AmlCode_ssdt5;
break;
}
memcpy(ssdtx, p, sizeof(acpi_header_t));
current += ssdtx->length;
memcpy(ssdtx, p, ssdtx->length);
update_ssdtx((void *)ssdtx, i);
ssdtx->checksum = 0;
ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
acpi_add_table(rsdp, ssdtx);
}
#endif
/* DSDT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * DSDT at %lx\n", current);
dsdt = (acpi_header_t *)current; // it will used by fadt
memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
current += dsdt->length;
memcpy(dsdt, &AmlCode, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length);
/* FACS */ // it needs 64 bit alignment
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
facs = (acpi_facs_t *) current; // it will be used by fadt
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
/* FDAT */
current = ( current + 0x07) & -0x08;
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
acpi_create_fadt(fadt, facs, dsdt);
acpi_add_table(rsdp, fadt);
#if DUMP_ACPI_TABLES == 1
printk(BIOS_DEBUG, "rsdp\n");
dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
printk(BIOS_DEBUG, "rsdt\n");
dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
printk(BIOS_DEBUG, "madt\n");
dump_mem(madt, ((void *)madt) + madt->header.length);
printk(BIOS_DEBUG, "srat\n");
dump_mem(srat, ((void *)srat) + srat->header.length);
printk(BIOS_DEBUG, "slit\n");
dump_mem(slit, ((void *)slit) + slit->header.length);
printk(BIOS_DEBUG, "ssdt\n");
dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
printk(BIOS_DEBUG, "fadt\n");
dump_mem(fadt, ((void *)fadt) + fadt->header.length);
#endif
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}

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src/mainboard/asus/m4a785-m/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {};

98
src/mainboard/asus/m4a785-m/cmos.layout Normal file
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entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
#96 288 r 0 temporary_filler
0 384 r 0 reserved_memory
384 1 e 4 boot_option
385 1 e 4 last_boot
386 1 e 1 ECC_memory
388 4 r 0 reboot_bits
392 3 e 5 baud_rate
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 h 0 boot_index
432 8 h 0 boot_countdown
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
5 0 115200
5 1 57600
5 2 38400
5 3 19200
5 4 9600
5 5 4800
5 6 2400
5 7 1200
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
#7 3 ROM
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums
checksum 392 983 984

105
src/mainboard/asus/m4a785-m/devicetree.cb Normal file
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chip northbridge/amd/amdfam10/root_complex
device lapic_cluster 0 on
chip cpu/amd/socket_AM3 #L1 and DDR2
device lapic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdfam10
device pci 18.0 on # northbridge
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
device pci 3.0 off end # PCIE P2P bridge 0x960b
device pci 4.0 off end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
device pci 9.0 off end #
device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet
register "gppsb_configuration" = "1" # Configuration B
register "gpp_configuration" = "3" # Configuration D default
register "port_enable" = "0x6fc"
register "gfx_dev2_dev3" = "1"
register "gfx_dual_slot" = "2"
register "gfx_lane_reversal" = "0"
register "gfx_tmds" = "0"
register "gfx_compliance" = "0"
register "gfx_reconfiguration" = "1"
register "gfx_link_width" = "0"
end
chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/ite/it8712f
device pnp 2e.0 off end # Floppy
device pnp 2e.1 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 off end # Environment Controller
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
end
device pnp 2e.8 off # MIDI
end
device pnp 2e.9 off # GAME
end
device pnp 2e.a off end # CIR
end #superio
end #LPC
device pci 14.4 on end # PCI to PCI Bridge [1002:4384]
device pci 14.5 on end # USB 2
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/sb700
end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
end # chip northbridge
end #pci_domain
end # northbridge/amd/amdfam10/root_complex

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src/mainboard/asus/m4a785-m/dsdt.asl Normal file
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src/mainboard/asus/m4a785-m/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* ACPI - create the Fixed ACPI Description Tables (FADT)
*/
#include <string.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/device.h>
#include "../../../southbridge/amd/sb700/sb700.h"
/*extern*/ u16 pm_base = 0x800;
/* pm_base should be set in sb acpi */
/* pm_base should be got from bar2 of rs780. Here I compact ACPI
* registers into 32 bytes limit.
* */
#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */
#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */
#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */
#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */
#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
pm_base &= 0xFFFF;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 0;
fadt->firmware_ctrl = (u32) facs;
fadt->dsdt = (u32) dsdt;
/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
fadt->preferred_pm_profile = 0x03;
fadt->sci_int = 9;
/* disable system management mode by setting to 0: */
fadt->smi_cmd = 0;
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF);
pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8);
pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF);
pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8);
pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF);
pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8);
pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF);
pm_iowrite(0x29, ACPI_GPE0_BLK >> 8);
/* CpuControl is in \_PR.CPU0, 6 bytes */
pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF);
pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8);
pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */
pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */
pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF);
pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8);
pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses
* the contents of the PM registers at
* index 20-2B to decode ACPI I/O address.
* AcpiSmiEn & SmiCmdEn*/
pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */
outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */
fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
fadt->pm1b_evt_blk = 0x0000;
fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
fadt->pm1b_cnt_blk = 0x0000;
fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
fadt->gpe0_blk = ACPI_GPE0_BLK;
fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */
fadt->pm1_evt_len = 4;
fadt->pm1_cnt_len = 2;
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0xe3;
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0; /* 0x7d these have to be */
fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch = 0x3; /* See table 5-11 */
fadt->flags = 0x0001c1a5;/* 0x25; */
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.resv = 0;
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
fadt->reset_value = 6;
fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
fadt->x_pm1b_evt_blk.bit_width = 4;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.resv = 0;
fadt->x_pm1b_evt_blk.addrl = 0x0;
fadt->x_pm1b_evt_blk.addrh = 0x0;
fadt->x_pm1a_cnt_blk.space_id = 1;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
fadt->x_pm1b_cnt_blk.bit_width = 2;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.resv = 0;
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.resv = 0;
fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
fadt->x_pm2_cnt_blk.addrh = 0x0;
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = 0;
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
* You may need to preset pci1234 for HTIO board,
* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
*/
u32 pci1234x[] = {
0x0000ff0,
};
/*
* HT Chain device num, actually it is unit id base of every ht device in chain,
* assume every chain only have 4 ht device at most
*/
u32 hcdnx[] = {
0x20202020,
};
u32 bus_type[256];
u32 sbdn_rs780;
u32 sbdn_sb700;
extern void get_pci1234(void);
static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 apicid_base;
device_t dev;
int i, j;
if (get_bus_conf_done == 1)
return; /* do it only once */
get_bus_conf_done = 1;
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
sbdn_rs780 = sysconf.sbdn;
sbdn_sb700 = 0;
for (i = 0; i < 2; i++) {
bus_sb700[i] = 0;
}
for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
bus_rs780[i] = 0;
}
for (i = 0; i < 256; i++) {
bus_type[i] = 0; /* default ISA bus. */
}
bus_type[0] = 1; /* pci */
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
bus_type[bus_rs780[0]] = 1;
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb700[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
/* rs780 */
for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
if(255 != bus_rs780[i]) {
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
bus_type[bus_rs780[i]] = 1; /* PCI bus. */
}
}
}
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_sb700 = apicid_base + 0;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 200x TODO <TODO@TODO>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * 19, /* Max. number of devices on the bus */
0x00, /* Interrupt router bus */
(0x14 << 3) | 0x3, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x1002, /* Vendor */
0x439d, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x8, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
{0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
{0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
{0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
{0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
{0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
{0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
{0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
{0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
#define ADT7461_write_byte(address, val) \
do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
#define SMBUS_IO_BASE 0x6000
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);
void set_pcie_reset(void);
u8 is_dev3_present(void);
void set_pcie_dereset()
{
u8 byte;
u16 word;
device_t sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
byte &= ~((1 << 1) | (1 << 2));
pm_iowrite(0x8d, byte);
/* set the GPM8 and GPM9 output enable and the value to 1 */
byte = pm_ioread(0x94);
byte &= ~((1 << 2) | (1 << 3));
byte |= ((1 << 0) | (1 << 1));
pm_iowrite(0x94, byte);
/* set the GPIO65 output enable and the value is 1 */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0x7e);
word |= (1 << 0);
word &= ~(1 << 4);
pci_write_config16(sm_dev, 0x7e, word);
}
void set_pcie_reset()
{
u8 byte;
u16 word;
device_t sm_dev;
/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
/* set 0 to bit2 :disable GPM8 as AZ_RST output */
byte = pm_ioread(0x8d);
byte &= ~((1 << 1) | (1 << 2));
pm_iowrite(0x8d, byte);
/* set the GPM8 and GPM9 output enable and the value to 0 */
byte = pm_ioread(0x94);
byte &= ~((1 << 2) | (1 << 3));
byte &= ~((1 << 0) | (1 << 1));
pm_iowrite(0x94, byte);
/* set the GPIO65 output enable and the value is 0 */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0x7e);
word &= ~(1 << 0);
word &= ~(1 << 4);
pci_write_config16(sm_dev, 0x7e, word);
}
#if 0 /* TODO: */
/********************************************************
* tilapia uses SB700 GPIO8 to detect IDE_DMA66.
* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
* get the cable type, 40 pin or 80 pin?
********************************************************/
static void get_ide_dma66(void)
{
u8 byte;
/*u32 sm_dev, ide_dev; */
device_t sm_dev, ide_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0xA9);
byte |= (1 << 4); /* Set Gpio8 as input */
pci_write_config8(sm_dev, 0xA9, byte);
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
byte = pci_read_config8(ide_dev, 0x56);
byte &= ~(7 << 0);
if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
byte |= 2 << 0; /* mode 2 */
else
byte |= 5 << 0; /* mode 5 */
pci_write_config8(ide_dev, 0x56, byte);
}
#endif
/*
* justify the dev3 is exist or not
* NOTE: This just copied from AMD Tilapia code.
* It is completly unknown it it will work at all for Asus M4A785-A
*/
u8 is_dev3_present(void)
{
u16 word;
device_t sm_dev;
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
/* put the GPIO68 output to tristate */
word = pci_read_config16(sm_dev, 0x7e);
word |= 1 << 6;
pci_write_config16(sm_dev, 0x7e,word);
/* read the GPIO68 input status */
word = pci_read_config16(sm_dev, 0x7e);
if(word & (1 << 10)){
/*not exist*/
return 0;
}else{
/*exist*/
return 1;
}
}
/*
* set thermal config
*/
static void set_thermal_config(void)
{
u8 byte;
u16 word;
device_t sm_dev;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
byte = ADT7461_read_byte(0x02); /* read status register to clear it */
ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte);
/* sb700 settings for thermal config */
/* set SB700 GPIO 64 to GPIO with pull-up */
byte = pm2_ioread(0x42);
byte &= 0x3f;
pm2_iowrite(0x42, byte);
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
byte &= 0xee;
pm2_iowrite(0xf0, byte);
/* set Talert to be active low */
byte = pm_ioread(0x67);
byte &= ~(1 << 5);
pm_iowrite(0x67, byte);
/* set Talert to generate ACPI event */
byte = pm_ioread(0x3c);
byte &= 0xf3;
pm_iowrite(0x3c, byte);
/* THERMTRIP pin */
/* byte = pm_ioread(0x68);
* byte |= 1 << 3;
* pm_iowrite(0x68, byte);
*
* byte = pm_ioread(0x55);
* byte |= 1 << 0;
* pm_iowrite(0x55, byte);
*
* byte = pm_ioread(0x67);
* byte &= ~( 1 << 6);
* pm_iowrite(0x67, byte);
*/
}
/*************************************************
* enable the dedicated function in m4a785m board.
* This function called early than rs780_enable.
*************************************************/
static void m4a785m_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard M4A785M Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM);
printk(BIOS_INFO,
"%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2);
printk(BIOS_INFO,
"%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
switch (msr.lo) {
case 0x10000000: /* 256M system memory */
uma_memory_size = 0x4000000; /* 64M recommended UMA */
break;
case 0x20000000: /* 512M system memory */
uma_memory_size = 0x8000000; /* 128M recommended UMA */
break;
default: /* 1GB and above system memory */
uma_memory_size = 0x10000000; /* 256M recommended UMA */
break;
}
uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
__func__, uma_memory_size, uma_memory_base);
/* TODO: TOP_MEM2 */
#else
uma_memory_size = 0x8000000; /* 128M recommended UMA */
uma_memory_base = 0x38000000; /* 1GB system memory supposed */
#endif
set_pcie_dereset();
/* get_ide_dma66(); */
set_thermal_config();
}
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD M4A785M Mainboard")
.enable_dev = m4a785m_enable,
};

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef MB_SYSCONF_H
#define MB_SYSCONF_H
struct mb_sysconf_t {
u8 bus_isa;
u8 bus_8132_0;
u8 bus_8132_1;
u8 bus_8132_2;
u8 bus_8111_0;
u8 bus_8111_1;
u8 bus_8132a[31][3];
u8 bus_8151[31][2];
u32 apicid_8111;
u32 apicid_8132_1;
u32 apicid_8132_2;
u32 apicid_8132a[31][2];
u32 sbdn3;
u32 sbdn3a[31];
u32 sbdn5[31];
u32 bus_type[256];
};
#endif

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "TILAPIA ";
struct mp_config_table *mc;
int j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
get_bus_conf();
/* Bus: Bus ID Type */
/* define bus and isa numbers */
for (j = 0; j < bus_isa; j++) {
smp_write_bus(mc, j, (char *)"PCI ");
}
smp_write_bus(mc, bus_isa, (char *)"ISA ");
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
u32 dword;
u8 byte;
dev =
dev_find_slot(bus_sb700[0],
PCI_DEVFN(sbdn_sb700 + 0x14, 0));
if (dev) {
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
/* Initialize interrupt mapping */
/* aza */
byte = pci_read_config8(dev, 0x63);
byte &= 0xf8;
byte |= 0; /* 0: INTA, ...., 7: INTH */
pci_write_config8(dev, 0x63, byte);
/* SATA */
dword = pci_read_config32(dev, 0xac);
dword &= ~(7 << 26);
dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
/* dword |= 1<<22; PIC and APIC co exists */
pci_write_config32(dev, 0xac, dword);
/*
* 00:12.0: PROG SATA : INT F
* 00:13.0: INTA USB_0
* 00:13.1: INTB USB_1
* 00:13.2: INTC USB_2
* 00:13.3: INTD USB_3
* 00:13.4: INTC USB_4
* 00:13.5: INTD USB2
* 00:14.1: INTA IDE
* 00:14.2: Prog HDA : INT E
* 00:14.5: INTB ACI
* 00:14.6: INTB MCI
*/
}
}
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#if CONFIG_GENERATE_ACPI_TABLES == 0
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
#define PCI_INT(bus, dev, fn, pin)
#endif
/* usb */
PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
PCI_INT(0x0, 0x12, 0x1, 0x11);
PCI_INT(0x0, 0x13, 0x0, 0x12);
PCI_INT(0x0, 0x13, 0x1, 0x13);
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* sata */
PCI_INT(0x0, 0x11, 0x0, 0x16);
/* HD Audio: b0:d20:f1:reg63 should be 0. */
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
/* configuration B doesnt need dev 5,6,7 */
/*
* PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
* PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
* PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
*/
PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}

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src/mainboard/asus/m4a785-m/resourcemap.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers
* F1:0x44 i = 0
* F1:0x4C i = 1
* F1:0x54 i = 2
* F1:0x5C i = 3
* F1:0x64 i = 4
* F1:0x6C i = 5
* F1:0x74 i = 6
* F1:0x7C i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 3] Reserved
* [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers
* F1:0x40 i = 0
* F1:0x48 i = 1
* F1:0x50 i = 2
* F1:0x58 i = 3
* F1:0x60 i = 4
* F1:0x68 i = 5
* F1:0x70 i = 6
* F1:0x78 i = 7
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 7: 2] Reserved
* [10: 8] Interleave Enable
* 000 = No interleave
* 001 = Interleave on A[12] (2 nodes)
* 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved
* 101 = reserved
* 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0
* F1:0x8C i = 1
* F1:0x94 i = 2
* F1:0x9C i = 3
* F1:0xA4 i = 4
* F1:0xAC i = 5
* F1:0xB4 i = 6
* F1:0xBC i = 7
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = Reserved
* [ 6: 6] Reserved
* [ 7: 7] Non-Posted
* 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
* F1:0x88 i = 1
* F1:0x90 i = 2
* F1:0x98 i = 3
* F1:0xA0 i = 4
* F1:0xA8 i = 5
* F1:0xB0 i = 6
* F1:0xB8 i = 7
* [ 0: 0] Read Enable
* 0 = Reads disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes disabled
* 1 = Writes Enabled
* [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock
* 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
* F1:0xCC i = 1
* F1:0xD4 i = 2
* F1:0xDC i = 3
* [ 2: 0] Destination Node ID
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 3: 3] Reserved
* [ 5: 4] Destination Link ID
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 = reserved
* [11: 6] Reserved
* [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers
* F1:0xC0 i = 0
* F1:0xC8 i = 1
* F1:0xD0 i = 2
* F1:0xD8 i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 3: 2] Reserved
* [ 4: 4] VGA Enable
* 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable
* 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair
* [11: 6] Reserved
* [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers
* F1:0xE0 i = 0
* F1:0xE4 i = 1
* F1:0xE8 i = 2
* F1:0xEC i = 3
* [ 0: 0] Read Enable
* 0 = Reads Disabled
* 1 = Reads Enabled
* [ 1: 1] Write Enable
* 0 = Writes Disabled
* 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved
* [ 6: 4] Destination Node
* 000 = Node 0
* 001 = Node 1
* 010 = Node 2
* 011 = Node 3
* 100 = Node 4
* 101 = Node 5
* 110 = Node 6
* 111 = Node 7
* [ 7: 7] Reserved
* [ 9: 8] Destination Link
* 00 = Link 0
* 01 = Link 1
* 10 = Link 2
* 11 - Reserved
* [15:10] Reserved
* [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
};
int max;
max = ARRAY_SIZE(register_values);
setup_resource_map(register_values, max);
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
//#define SYSTEM_TYPE 2 /* MOBILE */
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 1
#define SET_NB_CFG_54 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1
//used by incoherent_ht
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
//used by init_cpus and fidvid
#define SET_FIDVID 1
#define SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
static int smbus_read_byte(u32 device, u32 address);
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
{
int result;
result = smbus_read_byte(device, address);
return result;
}
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
//#include "spd_addr.h"
#define RC00 0
#define RC01 1
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
u32 val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sb700_pci_port80();
}
post_code(0x30);
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
/* All cores run this but the BSP(node0,core0) is the only core that returns. */
}
post_code(0x32);
enable_rs780_dev8();
sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
uart_init();
console_init();
printk(BIOS_DEBUG, "\n");
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// Load MPB
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
update_microcode(val);
post_code(0x33);
cpuSetAMDMSR();
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
/* Setup any mainboard PCI settings etc. */
setup_mb_resource_map();
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode.
I think it could be done by putting the spinlock flag in the cache
of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
/* run _early_setup before soft-reset. */
rs780_early_setup();
sb700_early_setup();
#if SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
rs780_htinit();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x40);
// die("Die Before MCT init.");
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
*/
// ram_check(0x00200000, 0x00200000 + (640 * 1024));
// ram_check(0x40200000, 0x40200000 + (640 * 1024));
// die("After MCT init before CAR disabled.");
rs780_before_pci_init();
sb700_before_pci_init();
post_code(0x42);
printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}

194
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/**
* This file defines the SPD addresses for the mainboard. Must be included in
* cache_as_ram_auto.c
*/
#define RC00 0
#define RC01 1
#define RC02 2
#define RC03 3
#define RC04 4
#define RC05 5
#define RC06 6
#define RC07 7
#define RC08 8
#define RC09 9
#define RC10 10
#define RC11 11
#define RC12 12
#define RC13 13
#define RC14 14
#define RC15 15
#define RC16 16
#define RC17 17
#define RC18 18
#define RC19 19
#define RC20 20
#define RC21 21
#define RC22 22
#define RC23 23
#define RC24 24
#define RC25 25
#define RC26 26
#define RC27 27
#define RC28 28
#define RC29 29
#define RC30 30
#define RC31 31
#define RC32 32
#define RC33 33
#define RC34 34
#define RC35 35
#define RC36 36
#define RC37 37
#define RC38 38
#define RC39 39
#define RC40 40
#define RC41 41
#define RC42 42
#define RC43 43
#define RC44 44
#define RC45 45
#define RC46 46
#define RC47 47
#define RC48 48
#define RC49 49
#define RC50 50
#define RC51 51
#define RC52 52
#define RC53 53
#define RC54 54
#define RC55 55
#define RC56 56
#define RC57 57
#define RC58 58
#define RC59 59
#define RC60 60
#define RC61 61
#define RC62 62
#define RC63 63
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#define DIMM4 0x54
#define DIMM5 0x55
#define DIMM6 0x56
#define DIMM7 0x57
static const u8 spd_addr[] = {
//first node
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node
RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 8
RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 12
RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 16
RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 20
RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 24
RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 32
RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 48
RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};