Update geode GX2 tree to match LX.
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Nils Jacobs
Patrick Georgi
parent
f3fe3d2140
commit
d0ac789e21
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@ -1,5 +1,4 @@
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chip northbridge/amd/gx2
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#register "irqmap" = "0xaa5b"
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device lapic 0 on end
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@ -5,7 +5,6 @@ chip northbridge/amd/gx2
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end
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end
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#register "irqmap" = "0xaa5b"
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/amd/cs5535
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@ -20,18 +20,10 @@
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##
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chip northbridge/amd/gx2
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register "irqmap" = "0xaa5b"
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device lapic 0 on end
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end
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end
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device pci_domain 0 on
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subsystemid 102d 0 inherit
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536
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device pci_domain 0 on
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device pci 1.0 on end # Geode GX2 Host Bridge
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device pci 1.1 on end # Geode GX2 Graphics Processor
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chip southbridge/amd/cs5536
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register "enable_gpio_int_route" = "0x0D0C0700"
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register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
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register "enable_USBP4_device" = "0" #0: host, 1:device
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@ -42,13 +34,19 @@ chip northbridge/amd/gx2
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register "com2_enable" = "0"
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register "com2_address" = "0x2F8"
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register "com2_irq" = "3"
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device pci e.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci e.0 on end # Realtek 8139 LAN
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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end
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end
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end
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end
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# APIC cluster is late CPU init.
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device lapic_cluster 0 on
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chip cpu/amd/model_gx2
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device lapic 0 on end
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end
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end
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end
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@ -1,6 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_amd_gx2_config
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{
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uint16_t irqmap;
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};
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extern struct chip_operations northbridge_amd_gx2_ops;
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@ -215,92 +215,6 @@ int sizeram(void)
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return sizem;
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}
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/* these are the 8-bit attributes for controlling RCONF registers */
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#define CACHE_DISABLE (1<<0)
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#define WRITE_ALLOCATE (1<<1)
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#define WRITE_PROTECT (1<<2)
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#define WRITE_THROUGH (1<<3)
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#define WRITE_COMBINE (1<<4)
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#define WRITE_SERIALIZE (1<<5)
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/* ram has none of this stuff */
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#define RAM_PROPERTIES (0)
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#define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE)
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#define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE)
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/* setup_gx2_cache
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*
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* Returns the amount of memory (in KB) available to the system. This is the
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* total amount of memory less the amount of memory reserved for SMM use.
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*/
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static int setup_gx2_cache(void)
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{
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msr_t msr;
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unsigned long long val;
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int sizekbytes, sizereg;
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sizekbytes = sizeram() * 1024;
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printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
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/* build up the rconf word. */
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/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
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/* set romrp */
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val = ((unsigned long long) ROM_PROPERTIES) << 56;
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/* make rom base useful for 1M roms */
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/* Flash base address -- sized for 1M for now */
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val |= ((unsigned long long) 0xfff00)<<36;
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/* set the devrp properties */
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val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
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/* Take our TOM, RIGHT shift 12, since it page-aligned, then LEFT-shift 8 for reg. */
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/* yank off memory for the SMM handler */
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sizekbytes -= SMM_SIZE;
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sizereg = sizekbytes;
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sizereg *= 1024; /* convert to bytes */
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sizereg >>= 12;
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sizereg <<= 8;
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val |= sizereg;
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val |= RAM_PROPERTIES;
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msr.lo = val;
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msr.hi = (val >> 32);
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printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
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wrmsr(CPU_RCONF_DEFAULT, msr);
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enable_cache();
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wbinvd();
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return sizekbytes;
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}
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/* we have to do this here. We have not found a nicer way to do it */
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static void setup_gx2(void)
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{
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unsigned long tmp, tmp2;
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msr_t msr;
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unsigned long size_kb, membytes;
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size_kb = setup_gx2_cache();
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membytes = size_kb * 1024;
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/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
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* so it is safe to use. You should NOT at this point call
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* sizeram() directly.
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*/
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/* fixme: SMM MSR 0x10000026 and 0x400000023 */
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/* calculate the OFFSET field */
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tmp = membytes - SMM_OFFSET;
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tmp >>= 12;
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tmp <<= 8;
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tmp |= 0x20000000;
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tmp |= (SMM_OFFSET >> 24);
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/* calculate the PBASE and PMASK fields */
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tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
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tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
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printk(BIOS_DEBUG, "MSR 0x%x is now 0x%lx:0x%lx\n", 0x10000026, tmp, tmp2);
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msr.hi = tmp;
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msr.lo = tmp2;
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wrmsr(0x10000026, msr);
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}
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static void enable_shadow(device_t dev)
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{
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@ -398,7 +312,6 @@ static void pci_domain_enable(device_t dev)
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northbridge_init_early();
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cpubug();
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chipsetinit();
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setup_gx2();
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print_conf();
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do_vsmbios();
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graphics_init();
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@ -1,3 +1,23 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Nils Jacobs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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@ -13,8 +33,6 @@
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#include <cpu/x86/msr.h>
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#include <cpu/x86/cache.h>
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/* put this here for now, we are not sure where it belongs */
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struct gliutable
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{
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unsigned long desc_name;
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@ -100,9 +118,6 @@ struct msrinit GeodeLinkPriorityTable[] = {
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{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
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};
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/* do we have dmi or not? assume NO per AMD */
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int havedmi = 0;
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static void writeglmsr(struct gliutable *gl)
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{
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msr_t msr;
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@ -110,10 +125,7 @@ static void writeglmsr(struct gliutable *gl)
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msr.lo = gl->lo;
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msr.hi = gl->hi;
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wrmsr(gl->desc_name, msr); /* MSR - see table above */
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printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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/* they do this, so we do this */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void ShadowInit(struct gliutable *gl)
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@ -127,133 +139,71 @@ static void ShadowInit(struct gliutable *gl)
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}
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}
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/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
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* CLEAN ME UP
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*/
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/* yes, this duplicates later code, but it seems that is how they want it done. */
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static void SysmemInit(struct gliutable *gl)
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{
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msr_t msr;
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int sizembytes, sizebytes;
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/* Figure out how much RAM is in the machine and alocate all to the
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* system. We will adjust for SMM and DMM now and Frame Buffer later.
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* system. We will adjust for SMM now and Frame Buffer later.
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*/
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sizembytes = sizeram();
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printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
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printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
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sizebytes = sizembytes << 20;
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sizebytes -= SMM_SIZE * 1024 + 1;
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sizebytes -= ((SMM_SIZE * 1024) + 1);
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if (havedmi)
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sizebytes -= DMM_SIZE * 1024 + 1;
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sizebytes -= 1;
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/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
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The top 8 bits go into 0-7 of msr.hi. */
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sizebytes --;
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msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
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/* set up sizebytes to fit into msr.lo */
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sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
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sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */
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sizebytes &= 0xfff00000;
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sizebytes |= 0x100;
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sizebytes |= 0x100; /* start at 1MB */
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msr.lo = sizebytes;
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wrmsr(gl->desc_name, msr); /* MSR - see table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
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gl->desc_name, msr.hi, msr.lo);
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}
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static void DMMGL0Init(struct gliutable *gl)
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{
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msr_t msr;
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int sizebytes = sizeram()<<20;
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long offset;
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if (! havedmi)
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return;
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printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
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sizebytes -= DMM_SIZE*1024;
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offset = sizebytes - DMM_OFFSET;
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printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
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offset >>= 12;
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msr.hi = (gl->hi) | (offset << 8);
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/* I don't think this is needed */
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msr.hi &= 0xffffff00;
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msr.hi |= (DMM_OFFSET >> 24);
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msr.lo = DMM_OFFSET << 8;
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msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void DMMGL1Init(struct gliutable *gl)
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{
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msr_t msr;
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if (! havedmi)
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return;
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printk(BIOS_DEBUG, "%s:\n", __func__ );
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msr.hi = gl->hi;
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/* I don't think this is needed */
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msr.hi &= 0xffffff00;
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msr.hi |= (DMM_OFFSET >> 24);
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msr.lo = DMM_OFFSET << 8;
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/* hmm. AMD source has SMM here ... SMM, not DMM? We think DMM */
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printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
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msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void SMMGL0Init(struct gliutable *gl)
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{
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msr_t msr;
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int sizebytes = sizeram() << 20;
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long offset;
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sizebytes -= SMM_SIZE * 1024;
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if (havedmi)
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sizebytes -= DMM_SIZE * 1024;
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sizebytes -= (SMM_SIZE * 1024);
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printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
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offset = sizebytes - SMM_OFFSET;
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printk(BIOS_DEBUG, "%s: offset is 0x%08lx\n", __func__, offset);
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offset >>= 12;
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offset = (offset >> 12) & 0x000fffff;
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printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
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msr.hi = offset << 8;
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msr.hi = offset << 8 | gl->hi;
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msr.hi |= SMM_OFFSET >> 24;
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msr.lo = SMM_OFFSET << 8;
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msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void SMMGL1Init(struct gliutable *gl)
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{
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msr_t msr;
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printk(BIOS_DEBUG, "%s:\n", __func__ );
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printk(BIOS_DEBUG, "%s:\n", __func__);
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msr.hi = gl->hi;
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/* I don't think this is needed */
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msr.hi &= 0xffffff00;
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msr.hi |= (SMM_OFFSET >> 24);
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msr.lo = SMM_OFFSET << 8;
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msr.lo = (SMM_OFFSET << 8) & 0xfff00000;
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msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void GLIUInit(struct gliutable *gl)
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@ -261,7 +211,6 @@ static void GLIUInit(struct gliutable *gl)
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while (gl->desc_type != GL_END) {
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switch (gl->desc_type) {
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default:
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/* For Unknown types: Write then read MSR */
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writeglmsr(gl);
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case SC_SHADOW: /* Check for a Shadow entry */
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ShadowInit(gl);
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@ -271,14 +220,6 @@ static void GLIUInit(struct gliutable *gl)
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SysmemInit(gl);
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break;
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case BMO_DMM: /* check for a DMM entry */
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DMMGL0Init(gl);
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break;
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|
||||
case BM_DMM: /* check for a DMM entry */
|
||||
DMMGL1Init(gl);
|
||||
break;
|
||||
|
||||
case BMO_SMM: /* check for a SMM entry */
|
||||
SMMGL0Init(gl);
|
||||
break;
|
||||
|
|
@ -333,8 +274,7 @@ static void GLPCIInit(void)
|
|||
* so we need a high page aligned addresss (pah) and low page aligned address (pal)
|
||||
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
|
||||
*/
|
||||
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
|
||||
pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
|
||||
pah = ((msr.hi & 0xff) << 12) | ((msr.lo >> 20) & 0xfff);
|
||||
/* we have the page address. Now make it a page-aligned address */
|
||||
pah <<= 12;
|
||||
|
||||
|
|
@ -342,7 +282,7 @@ static void GLPCIInit(void)
|
|||
msr.hi = pah;
|
||||
msr.lo = pal;
|
||||
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
|
||||
printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
|
||||
printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
|
||||
msrnum = GLPCI_RC1;
|
||||
wrmsr(msrnum, msr);
|
||||
}
|
||||
|
|
@ -351,6 +291,7 @@ static void GLPCIInit(void)
|
|||
msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
|
||||
msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
|
||||
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
|
||||
printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
|
||||
msrnum = GLPCI_RC2;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
|
@ -393,7 +334,9 @@ static void GLPCIInit(void)
|
|||
|
||||
/* we are ignoring the 5530 case for now, and perhaps forever. */
|
||||
|
||||
/* 5535 NB Init */
|
||||
/* 553X NB Init */
|
||||
|
||||
/* Arbiter setup */
|
||||
msrnum = GLPCI_ARB;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
|
||||
|
|
@ -449,33 +392,10 @@ static void ClockGatingInit(void)
|
|||
struct msrinit *gating = ClockGatingDefault;
|
||||
int i;
|
||||
|
||||
#if 0
|
||||
mov cx, TOKEN_CLK_GATE
|
||||
NOSTACK bx, GetNVRAMValueBX
|
||||
cmp al, TVALUE_CG_OFF
|
||||
je gatingdone
|
||||
|
||||
cmp al, TVALUE_CG_DEFAULT
|
||||
jb allon
|
||||
ja performance
|
||||
lea si, ClockGatingDefault
|
||||
jmp nextdevice
|
||||
|
||||
allon:
|
||||
lea si, ClockGatingAllOn
|
||||
jmp nextdevice
|
||||
|
||||
performance:
|
||||
lea si, ClockGatingPerformance
|
||||
#endif
|
||||
|
||||
for(i = 0; gating->msrnum != 0xffffffff; i++) {
|
||||
for (i = 0; gating->msrnum != 0xffffffff; i++) {
|
||||
msr = rdmsr(gating->msrnum);
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
|
||||
msr.hi |= gating->msr.hi;
|
||||
msr.lo |= gating->msr.lo;
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
|
||||
gating->msrnum, msr.hi, msr.lo);
|
||||
wrmsr(gating->msrnum, msr); /* MSR - See the table above */
|
||||
gating += 1;
|
||||
}
|
||||
|
|
@ -484,17 +404,15 @@ performance:
|
|||
static void GeodeLinkPriority(void)
|
||||
{
|
||||
msr_t msr = { 0, 0 };
|
||||
|
||||
struct msrinit *prio = GeodeLinkPriorityTable;
|
||||
int i;
|
||||
|
||||
for (i = 0; prio->msrnum != 0xffffffff; i++) {
|
||||
msr = rdmsr(prio->msrnum);
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
|
||||
msr.hi |= prio->msr.hi;
|
||||
msr.lo &= ~0xfff;
|
||||
msr.lo |= prio->msr.lo;
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
|
||||
prio->msrnum, msr.hi, msr.lo);
|
||||
wrmsr(prio->msrnum, msr); /* MSR - See the table above */
|
||||
prio += 1;
|
||||
}
|
||||
|
|
@ -507,8 +425,8 @@ static void GeodeLinkPriority(void)
|
|||
*/
|
||||
static uint64_t getShadow(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr_t msr = { 0, 0 };
|
||||
|
||||
msr = rdmsr(GLIU0_P2D_SC_0);
|
||||
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
|
||||
}
|
||||
|
|
@ -614,8 +532,7 @@ static void setShadow(uint64_t shadowSettings)
|
|||
}
|
||||
}
|
||||
|
||||
/* Set up a stack for ease of further testing. */
|
||||
static void shadowRom(void)
|
||||
static void rom_shadow_settings(void)
|
||||
{
|
||||
uint64_t shadowSettings = getShadow();
|
||||
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */
|
||||
|
|
@ -637,7 +554,7 @@ static void shadowRom(void)
|
|||
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
|
||||
#define ROMRC_RCONF_DEFAULT 0x25
|
||||
|
||||
static void RCONFInit(void)
|
||||
static void enable_L_cache(void)
|
||||
{
|
||||
struct gliutable *gl = 0;
|
||||
int i;
|
||||
|
|
@ -657,7 +574,6 @@ static void RCONFInit(void)
|
|||
}
|
||||
|
||||
/* sysdescfound: */
|
||||
/* found the descriptor... get its contents */
|
||||
msr = rdmsr(gl->desc_name);
|
||||
|
||||
/* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the
|
||||
|
|
@ -668,10 +584,10 @@ static void RCONFInit(void)
|
|||
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */
|
||||
|
||||
/* Set Default SYSMEM region properties */
|
||||
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* 8 (or ~8) */
|
||||
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* NOT writethrough == writeback 8 (or ~8) */
|
||||
|
||||
/* Set PCI space cache properties */
|
||||
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* only need the bottom bits and lets clean the rest of edx */
|
||||
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* setting is split betwwen hi and lo... */
|
||||
msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
|
||||
|
||||
/* Set the ROMBASE. This is usually FFFC0000h */
|
||||
|
|
@ -682,14 +598,33 @@ static void RCONFInit(void)
|
|||
|
||||
/* now program RCONF_DEFAULT */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, msr.lo);
|
||||
|
||||
/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
|
||||
/* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */
|
||||
/* Set to match system memory cache properties. */
|
||||
msr = rdmsr(CPU_RCONF_DEFAULT);
|
||||
SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
|
||||
msr = rdmsr(CPU_RCONF_BYPASS);
|
||||
msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
|
||||
wrmsr(CPU_RCONF_BYPASS, msr);
|
||||
printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
|
||||
}
|
||||
|
||||
static void setup_gx2_cache(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
enable_L_cache();
|
||||
|
||||
/* Make sure all INVD instructions are treated as WBINVD. We do this
|
||||
* because we've found some programs which require this behavior.
|
||||
*/
|
||||
msr = rdmsr(CPU_DM_CONFIG0);
|
||||
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
|
||||
wrmsr(CPU_DM_CONFIG0, msr);
|
||||
|
||||
x86_enable_cache();
|
||||
wbinvd();
|
||||
}
|
||||
|
||||
uint32_t get_systop(void)
|
||||
|
|
@ -719,36 +654,27 @@ uint32_t get_systop(void)
|
|||
/* Core Logic initialization: Host bridge. */
|
||||
void northbridge_init_early(void)
|
||||
{
|
||||
msr_t msr;
|
||||
int i;
|
||||
printk(BIOS_DEBUG, "Enter %s\n", __func__);
|
||||
|
||||
for (i = 0; gliutables[i]; i++)
|
||||
GLIUInit(gliutables[i]);
|
||||
|
||||
GeodeLinkPriority();
|
||||
|
||||
shadowRom();
|
||||
|
||||
RCONFInit();
|
||||
|
||||
/* The cacheInit function in GeodeROM tests cache and, among other things,
|
||||
* makes sure all INVD instructions are treated as WBINVD. We do this
|
||||
* because we've found some programs which require this behavior.
|
||||
* That subset of cacheInit() is implemented here:
|
||||
*/
|
||||
msr = rdmsr(CPU_DM_CONFIG0);
|
||||
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
|
||||
wrmsr(CPU_DM_CONFIG0, msr);
|
||||
|
||||
/* Now that the descriptor to memory is set up. */
|
||||
/* The memory controller needs one read to synch its lines before it can be used. */
|
||||
i = *(int *) 0;
|
||||
|
||||
GeodeLinkPriority();
|
||||
|
||||
setup_gx2_cache();
|
||||
|
||||
rom_shadow_settings();
|
||||
|
||||
GLPCIInit();
|
||||
|
||||
ClockGatingInit();
|
||||
__asm__("FINIT\n");
|
||||
/* CPUBugsFix -- called elsewhere */
|
||||
|
||||
__asm__ __volatile__("FINIT\n");
|
||||
printk(BIOS_DEBUG, "Exit %s\n", __func__);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue