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intel/fsp1_1: Declare fsp_load() as static 

The function has only one local call-site.

Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-01-10 00:23:58 +02:00
parent ae38035d3a
commit d0bc92df73
2 changed files with 1 additions and 13 deletions
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6
src/drivers/intel/fsp1_1/include/fsp/ramstage.h
View File

@ -6,12 +6,6 @@
#include <fsp/util.h>
#include <stdint.h>
/*
* Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately
* from calling silicon init. It might be required in cases where stage cache is
* no longer available by the point SoC calls into silicon init.
*/
void fsp_load(void);
/* Perform Intel silicon init. */
void intel_silicon_init(void);
void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);

8
src/drivers/intel/fsp1_1/ramstage.c
View File

@ -173,15 +173,11 @@ static int fsp_find_and_relocate(struct prog *fsp)
return 0;
}
void fsp_load(void)
static void fsp_load(void)
{
static int load_done;
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
int is_s3_wakeup = acpi_is_wakeup_s3();
if (load_done)
return;
if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsp);
@ -192,8 +188,6 @@ void fsp_load(void)
/* FSP_INFO_HEADER is set as the program entry. */
fsp_update_fih(prog_entry(&fsp));
load_done = 1;
}
void intel_silicon_init(void)