From d0eeba38de1e824dc8827e2d060cb6b995a9e821 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 14 Jul 2023 19:50:54 +0000 Subject: [PATCH] mb/google/rex/var/ovis: Update the Type-C USB2/3 port mapping This patch updates the Type-C USB2/3 port mapping to reflect the mux connection change as mentioned in previous patch commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux change as per schematics). Here is the correct port mapping after considering the mux swap: +--------------------------------+-------------+---------------+ | TCSS-USB Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | +------------------+-------------+-------------+---------------+ BUG=b:289300284 TEST=Able to build and boot google/ovis to get display over Type-C1 and Type-C2 port. Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464 Reviewed-by: Paul Menzel Reviewed-by: Nick Vaccaro Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- .../google/rex/variants/ovis/overridetree.cb | 40 +++++++++---------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 112072cb97..492ab154b2 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/meteorlake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2 @@ -98,14 +98,14 @@ chip soc/intel/meteorlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))" - device ref tcss_usb3_port2 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port1 on end end end end @@ -145,27 +145,27 @@ chip soc/intel/meteorlake register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref usb2_port1 on end + device ref usb2_port3 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))" - device ref usb2_port3 on end + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port4 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A1"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 2))" register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb2_port7 on end end @@ -173,28 +173,28 @@ chip soc/intel/meteorlake register "desc" = ""USB2 Type-A Port A2"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(3, 3))" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(4, 3))" device ref usb2_port8 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A3"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(3, 4))" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 4))" device ref usb2_port9 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A1"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(4, 2))" register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb3_port2 on end end @@ -232,15 +232,15 @@ chip soc/intel/meteorlake use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end - chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port - device generic 2 alias conn1 on end - end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port2 as usb3_port - device generic 1 alias conn2 on end + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 2 alias conn2 on end end end end