GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/haswell: Decouple mainboard USB config from MRC 

With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2021-03-12 14:20:05 +01:00 committed by Patrick Georgi
parent 6902263dca
commit d0f971fe9a
15 changed files with 109 additions and 43 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/asrock/b85m_pro4/romstage.c
View File

@ -25,7 +25,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@ -43,7 +43,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },

4
src/mainboard/asrock/h81m-hds/romstage.c
View File

@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@ -41,7 +41,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 },
{ 1, 0 },

4
src/mainboard/google/beltino/romstage.c
View File

@ -46,7 +46,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */
USB_PORT_MINI_PCIE },
@ -66,7 +66,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; CN22 */
{ 1, 1 }, /* P2; CN23 */

4
src/mainboard/google/slippy/variants/falco/romstage.c
View File

@ -25,7 +25,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: Port A, CN8 */
USB_PORT_BACK_PANEL },
@ -45,7 +45,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_INTERNAL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN8 */
{ 1, 0 }, /* P2; Port B, CN9 */

4
src/mainboard/google/slippy/variants/leon/romstage.c
View File

@ -19,7 +19,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
return !(spd_index & 0x4);
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@ -39,7 +39,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */

4
src/mainboard/google/slippy/variants/peppy/romstage.c
View File

@ -32,7 +32,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
USB_PORT_MINI_PCIE },
@ -52,7 +52,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN6 */
{ 0, USB_OC_PIN_SKIP }, /* P2; */

4
src/mainboard/google/slippy/variants/wolf/romstage.c
View File

@ -25,7 +25,7 @@ bool variant_is_dual_channel(const unsigned int spd_index)
}
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Port A, CN10 */
USB_PORT_BACK_PANEL },
@ -45,7 +45,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_SKIP },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; Port A, CN10 */
{ 1, 2 }, /* P2; Port B, CN11 */

4
src/mainboard/hp/folio_9480m/romstage.c
View File

@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* dock */
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */
@ -35,7 +35,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, USB_OC_PIN_SKIP }, /* dock */
{ 1, USB_OC_PIN_SKIP }, /* left */
{ 1, USB_OC_PIN_SKIP }, /* right */

4
src/mainboard/intel/baskingridge/romstage.c
View File

@ -49,7 +49,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
USB_PORT_BACK_PANEL },
@ -81,7 +81,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
USB_PORT_FRONT_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */

4
src/mainboard/lenovo/t440p/romstage.c
View File

@ -46,7 +46,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x51;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
@ -64,7 +64,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, USB_OC_PIN_SKIP },

4
src/mainboard/msi/h81m-p33/romstage.c
View File

@ -23,7 +23,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[2] = 0x52;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@ -41,7 +41,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 0 },
{ 1, 0 },
{ 1, 1 },

4
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -25,7 +25,7 @@ void mb_get_spd_map(struct spd_info *spdi)
spdi->addresses[3] = 0x53;
}
const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, USB_PORT_INTERNAL },
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL },
@ -43,7 +43,7 @@ const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = {
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
};
const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = {
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */
{ 1, 1 },
{ 1, 1 },

26
src/northbridge/intel/haswell/pei_data.h
View File

@ -10,30 +10,30 @@ typedef void (*tx_byte_func)(unsigned char byte);
#define SPD_LEN 256
#define USB_OC_PIN_SKIP 8
#define PEI_USB_OC_PIN_SKIP 8
enum usb2_port_location {
USB_PORT_BACK_PANEL = 0,
USB_PORT_FRONT_PANEL,
USB_PORT_DOCK,
USB_PORT_MINI_PCIE,
USB_PORT_FLEX,
USB_PORT_INTERNAL,
USB_PORT_SKIP
enum pei_usb2_port_location {
PEI_USB_PORT_BACK_PANEL = 0,
PEI_USB_PORT_FRONT_PANEL,
PEI_USB_PORT_DOCK,
PEI_USB_PORT_MINI_PCIE,
PEI_USB_PORT_FLEX,
PEI_USB_PORT_INTERNAL,
PEI_USB_PORT_SKIP
};
/* Usb Port Length:
* [16:4] = length in inches in octal format
* [3:0] = decimal point
*/
struct usb2_port_setting {
struct pei_usb2_port_setting {
uint16_t length;
uint8_t enable;
uint8_t over_current_pin;
uint8_t location;
} __packed;
struct usb3_port_setting {
struct pei_usb3_port_setting {
uint8_t enable;
uint8_t over_current_pin;
} __packed;
@ -80,8 +80,8 @@ struct pei_data
uint32_t max_ddr3_freq;
/* Route all USB ports to XHCI controller in resume path */
int usb_xhci_on_resume;
struct usb2_port_setting usb2_ports[16];
struct usb3_port_setting usb3_ports[16];
struct pei_usb2_port_setting usb2_ports[16];
struct pei_usb3_port_setting usb3_ports[16];
uint8_t spd_data[4][SPD_LEN];
tx_byte_func tx_byte;
} __packed;

41
src/northbridge/intel/haswell/raminit.c
View File

@ -309,6 +309,25 @@ static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
}
static enum pei_usb2_port_location map_to_pei_usb2_location(const enum usb2_port_location loc)
{
static const enum pei_usb2_port_location map[] = {
[USB_PORT_SKIP] = PEI_USB_PORT_SKIP,
[USB_PORT_BACK_PANEL] = PEI_USB_PORT_BACK_PANEL,
[USB_PORT_FRONT_PANEL] = PEI_USB_PORT_FRONT_PANEL,
[USB_PORT_DOCK] = PEI_USB_PORT_DOCK,
[USB_PORT_MINI_PCIE] = PEI_USB_PORT_MINI_PCIE,
[USB_PORT_FLEX] = PEI_USB_PORT_FLEX,
[USB_PORT_INTERNAL] = PEI_USB_PORT_INTERNAL,
};
return loc >= ARRAY_SIZE(map) ? PEI_USB_PORT_SKIP : map[loc];
}
static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
{
return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
}
void perform_raminit(const int s3resume)
{
const struct device *gbe = pcidev_on_root(0x19, 0);
@ -337,8 +356,26 @@ void perform_raminit(const int s3resume)
.usb_xhci_on_resume = cfg->usb_xhci_on_resume,
};
memcpy(pei_data.usb2_ports, mainboard_usb2_ports, sizeof(mainboard_usb2_ports));
memcpy(pei_data.usb3_ports, mainboard_usb3_ports, sizeof(mainboard_usb3_ports));
for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb2_ports); i++) {
/* If a port is not enabled, skip it */
if (!mainboard_usb2_ports[i].enable) {
pei_data.usb2_ports[i].over_current_pin = PEI_USB_OC_PIN_SKIP;
pei_data.usb2_ports[i].location = PEI_USB_PORT_SKIP;
continue;
}
const enum usb2_port_location loc = mainboard_usb2_ports[i].location;
const uint8_t oc_pin = mainboard_usb2_ports[i].oc_pin;
pei_data.usb2_ports[i].length = mainboard_usb2_ports[i].length;
pei_data.usb2_ports[i].enable = mainboard_usb2_ports[i].enable;
pei_data.usb2_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
pei_data.usb2_ports[i].location = map_to_pei_usb2_location(loc);
}
for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb3_ports); i++) {
const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin;
pei_data.usb3_ports[i].enable = mainboard_usb3_ports[i].enable;
pei_data.usb3_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
}
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
pei_data.boot_mode = s3resume ? 2 : 0;

37
src/northbridge/intel/haswell/raminit.h
View File

@ -3,8 +3,7 @@
#ifndef RAMINIT_H
#define RAMINIT_H
#include <stdint.h>
#include "pei_data.h"
#include <types.h>
#define SPD_MEMORY_DOWN 0xff
@ -21,9 +20,39 @@ struct spd_info {
#define MAX_USB3_PORTS 6
#endif
/* There are 8 OC pins */
#define USB_OC_PIN_SKIP 8
enum usb2_port_location {
USB_PORT_SKIP = 0,
USB_PORT_BACK_PANEL,
USB_PORT_FRONT_PANEL,
USB_PORT_DOCK,
USB_PORT_MINI_PCIE,
USB_PORT_FLEX,
USB_PORT_INTERNAL,
};
/*
* USB port length is in MRC format: binary-coded decimal length in tenths of an inch.
* 4.2 inches -> 0x0042
* 12.7 inches -> 0x0127
*/
struct usb2_port_config {
uint16_t length;
bool enable;
unsigned short oc_pin;
enum usb2_port_location location;
};
struct usb3_port_config {
bool enable;
unsigned int oc_pin;
};
/* Mainboard-specific USB configuration */
extern const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS];
extern const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS];
extern const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS];
extern const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS];
/* Mainboard callback to fill in the SPD addresses */
void mb_get_spd_map(struct spd_info *spdi);