soc/intel/common: Implement IOC driver

Starting with Meteor Lake SoC, the PCR/DMI interface to program GPMR
is replaced with IOC (I/O Cache), hence, this patch implements IOC
driver to support that migration.

Reference: 643504 MTL FAS section 7.5.2

TEST=Build and boot to OS for TGL RVP and MTL PSS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63198
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/gpmr/gpmr.c

@@ -2,24 +2,34 @@
 
 #include <console/console.h>
 #include <intelblocks/gpmr.h>
+#include <intelblocks/ioc.h>
 #include <intelblocks/pcr.h>
 #include <soc/pcr_ids.h>
 
 /* GPMR Register read given offset */
 uint32_t gpmr_read32(uint16_t offset)
 {
-	return pcr_read32(PID_DMI, offset);
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC))
+		return ioc_reg_read32(offset);
+	else
+		return pcr_read32(PID_DMI, offset);
 }
 
 /* GPMR Register write given offset and val */
 void gpmr_write32(uint16_t offset, uint32_t val)
 {
-	return pcr_write32(PID_DMI, offset, val);
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC))
+		return ioc_reg_write32(offset, val);
+	else
+		return pcr_write32(PID_DMI, offset, val);
 }
 
 void gpmr_or32(uint16_t offset, uint32_t ordata)
 {
-	return pcr_or32(PID_DMI, offset, ordata);
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC))
+		return ioc_reg_or32(offset, ordata);
+	else
+		return pcr_or32(PID_DMI, offset, ordata);
 }
 
 /* Check for available free gpmr */

src/soc/intel/common/block/include/intelblocks/gpmr.h

@@ -4,7 +4,11 @@
 #define SOC_INTEL_COMMON_BLOCK_GPMR_H
 
 #include <types.h>
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)
+#include <intelblocks/ioc_gpmr.h>
+#else
 #include <intelblocks/pcr_gpmr.h>
+#endif
 
 uint32_t gpmr_read32(uint16_t offset);
 void gpmr_write32(uint16_t offset, uint32_t val);

src/soc/intel/common/block/include/intelblocks/ioc.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_IOC_H
+#define SOC_INTEL_COMMON_BLOCK_IOC_H
+
+#include <types.h>
+
+void ioc_reg_write32(uint32_t offset, uint32_t value);
+uint32_t ioc_reg_read32(uint32_t offset);
+void ioc_reg_or32(uint32_t offset, uint32_t ordata);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_IOC_H */

src/soc/intel/common/block/include/intelblocks/ioc_gpmr.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_IOC_GPMR_H
+#define SOC_INTEL_COMMON_BLOCK_IOC_GPMR_H
+#include <assert.h>
+
+#define GPMR_LPCLGIR1		0x7a30
+#define GPMR_LPCGMR		0x7a40
+#define GPMR_GCS		0x7a4c
+#define  GPMR_GCS_BILD		0x1
+#define GPMR_LPCIOD		0x7a70
+#define GPMR_LPCIOE		0x7a74
+#define GPMR_TCOBASE		0x7a78
+#define  GPMR_TCOEN		(1 << 1)
+
+#define MAX_GPMR_REGS		3
+
+#define GPMR_OFFSET(x)		(0x7a7c + (x) * 8)
+#define  GPMR_LIMIT_MASK	0xffff0000
+#define  GPMR_BASE_SHIFT	16
+#define  GPMR_BASE_MASK		0xffff
+
+#define GPMR_DID_OFFSET(x)	(0x7a80 + (x) * 8)
+#define  GPMR_EN		BIT(31)
+
+#define GPMR_DMICTL		dead_code_t(unsigned int)
+#define  GPMR_DMICTL_SRLOCK	dead_code_t(unsigned int)
+
+#endif

src/soc/intel/common/block/ioc/Kconfig

@@ -0,0 +1,7 @@
+config SOC_INTEL_COMMON_BLOCK_IOC
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_SA
+	help
+	  Intel Processor common IO Cache (IOC).
+	  IOC will replace DMI interface starting with Meteor Lake SoC
+	  (which does not have the PCH die).

src/soc/intel/common/block/ioc/Makefile.inc

@@ -0,0 +1,3 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c
+romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_IOC) += ioc.c

src/soc/intel/common/block/ioc/ioc.c

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <intelblocks/ioc.h>
+#include <soc/iomap.h>
+
+void ioc_reg_write32(uint32_t offset, uint32_t value)
+{
+	write32p(MCH_BASE_ADDRESS + offset, value);
+}
+
+uint32_t ioc_reg_read32(uint32_t offset)
+{
+	return read32p(MCH_BASE_ADDRESS + offset);
+}
+
+void ioc_reg_or32(uint32_t offset, uint32_t ordata)
+{
+	uint32_t data32;
+
+	data32 = read32p(MCH_BASE_ADDRESS + offset);
+	data32 |= ordata;
+	write32p(MCH_BASE_ADDRESS + offset, data32);
+}

src/soc/intel/common/pch/lockdown/lockdown.c

@@ -30,7 +30,7 @@ int get_lockdown_config(void)
 static void gpmr_lockdown_cfg(void)
 {
 	/*
-	 * GCS reg of DMI
+	 * GCS reg
 	 *
 	 * When set, prevents GCS.BBS from being changed
 	 * GCS.BBS: (Boot BIOS Strap) This field determines the destination
@@ -43,9 +43,10 @@ static void gpmr_lockdown_cfg(void)
 
 	/*
 	 * Set Secure Register Lock (SRL) bit in DMI control register to lock
-	 * DMI configuration.
+	 * DMI configuration and bypass when IOC instead of DMI
 	 */
-	gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK);
+	if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IOC))
+		gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK);
 }
 
 static void fast_spi_lockdown_cfg(int chipset_lockdown)