diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index 7b6d8fed8f..aa75a64f4f 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -49,7 +49,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
 u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
 {
 	/*get BAR3 base address for nbcfg0x1c */
-	u32 addr = pci_read_config32(nb_dev, 0x1c);
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
 	printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);
 	addr |= dev->bus->secondary << 20 |	/* bus num */
@@ -62,7 +62,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
 	u32 reg_old, reg;
 
 	/*get BAR3 base address for nbcfg0x1c */
-	u32 addr = pci_read_config32(nb_dev, 0x1c);
+	u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
 	/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
 		     dev->path.pci.devfn);*/
 	addr |= dev->bus->secondary << 20 |	/* bus num */
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index e0fc59d5cf..12fea1f2c9 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -212,8 +212,8 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 << 0, 1 << 0);	/* no description in datasheet. */
 
 	/* init GPPSB port */
-	/* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 0*/
-	set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16);
+	/* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101 and shortens the enumeration timer by setting bit[19] to 1*/
+	set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16);
 	/* PCIE initialization 5.10.2: rpr 2.4 */
 	set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
 	/* Do not gate the electrical idle from the PHY and enables the escape from L1L23 */
@@ -240,7 +240,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	}
 
 	/* step 5: dynamic slave CPL buffer allocation */
-	set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
+	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 11, 1 << 11);
 
 	/* step 5a: Training for GPP devices */
 	/* init GPP */