Rename AMD_AGESA to CPU_AMD_AGESA

Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
the explicit selects from the mainboards.

Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/792
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Kyösti Mälkki 2012-03-16 15:40:56 +02:00 committed by Patrick Georgi
parent f5bb4771de
commit d11ca1d08d
13 changed files with 12 additions and 33 deletions

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@ -51,5 +51,5 @@ SECTIONS
*(.eh_frame); *(.eh_frame);
} }
_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage"); _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
} }

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@ -14,4 +14,4 @@ subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
subdirs-$(CONFIG_CPU_AMD_SC520) += sc520 subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
subdirs-$(CONFIG_AMD_AGESA) += agesa subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa

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@ -17,12 +17,15 @@
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
# #
config AMD_AGESA config CPU_AMD_AGESA
bool bool
default y if CPU_AMD_AGESA_FAMILY10
default y if CPU_AMD_AGESA_FAMILY12
default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15 default y if CPU_AMD_AGESA_FAMILY15
default n default n
if AMD_AGESA if CPU_AMD_AGESA
config XIP_ROM_SIZE config XIP_ROM_SIZE
hex hex
@ -40,5 +43,5 @@ source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig source src/cpu/amd/agesa/family15/Kconfig
endif # AMD_AGESA endif # CPU_AMD_AGESA

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@ -3,7 +3,7 @@
ramstage-y += reset.c ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code #SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y) ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c

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@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select ENABLE_APIC_EXT_ID select ENABLE_APIC_EXT_ID
select GFXUMA select GFXUMA
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/inagua default amd/inagua

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@ -42,10 +42,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select GFXUMA select GFXUMA
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/persimmon default amd/persimmon

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@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select GFXUMA select GFXUMA
select UDELAY_LAPIC select UDELAY_LAPIC
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/south_station default amd/south_station

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@ -45,10 +45,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select ENABLE_APIC_EXT_ID select ENABLE_APIC_EXT_ID
select GFXUMA select GFXUMA
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/torpedo default amd/torpedo

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@ -42,10 +42,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select GFXUMA select GFXUMA
select UDELAY_LAPIC select UDELAY_LAPIC
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default amd/union_station default amd/union_station

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@ -43,10 +43,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_4096 select BOARD_ROMSIZE_KB_4096
select GFXUMA select GFXUMA
config AMD_AGESA
bool
default y
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default asrock/e350m1 default asrock/e350m1

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@ -1,7 +1,7 @@
ramstage-y += reset.c ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code #SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y) ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c

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@ -3,7 +3,7 @@
ramstage-y += reset.c ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code #SB800 CIMx share AGESA V5 lib code
ifneq ($(CONFIG_AMD_AGESA),y) ifneq ($(CONFIG_CPU_AMD_AGESA),y)
AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c

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@ -19,7 +19,7 @@
config NORTHBRIDGE_AMD_AGESA config NORTHBRIDGE_AMD_AGESA
bool bool
default AMD_AGESA default CPU_AMD_AGESA
if NORTHBRIDGE_AMD_AGESA if NORTHBRIDGE_AMD_AGESA