{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC

FSP logo handling used FspsConfig.LogoPtr and FspsConfig.LogoSize which
are chipset specific.

Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.

BUG=NA
TEST= Build and verified logo is displayed on Facebook Monolith

Change-Id: I30c7bdc0532ff8823e06f4136f210b542385d5ce
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37792
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/fsp2_0/Kconfig

@@ -156,10 +156,14 @@ config FSP_PEIM_TO_PEIM_INTERFACE
 	  is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
 	  useful to add further PPI if required.
 
+config HAVE_FSP_LOGO_SUPPORT
+	bool
+	default n
+
 config FSP2_0_DISPLAY_LOGO
 	bool "Enable logo"
 	default n
-	depends on HAVE_FSP_GOP
+	depends on HAVE_FSP_LOGO_SUPPORT
 	help
 	  Uses the FSP to display the boot logo. This method supports a
 	  BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed

src/drivers/intel/fsp2_0/include/fsp/api.h

@@ -70,13 +70,15 @@ uint8_t fsp_memory_mainboard_version(void);
 uint8_t fsp_memory_soc_version(void);
 
 /* Load logo to be displayed by FSP */
-void load_logo(FSPS_UPD *supd);
+const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size);
 
 /* Callback after processing FSP notify */
 void platform_fsp_notify_status(enum fsp_notify_phase phase);
 
 /* Initialize memory margin analysis settings. */
 void setup_mma(FSP_M_CONFIG *memory_cfg);
+/* Update the SOC specific logo param and load the logo. */
+const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd);
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);

src/drivers/intel/fsp2_0/logo.c

@@ -11,17 +11,24 @@
  * GNU General Public License for more details.
  */
 
-#include <soc/ramstage.h>
+#include <cbfs.h>
-#include <console/console.h>
+#include <cbmem.h>
 #include <fsp/api.h>
-#include <include/cbfs.h>
 
-void load_logo(FSPS_UPD *supd)
+const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size)
 {
-	FSP_S_CONFIG *params = &supd->FspsConfig;
+	const struct cbmem_entry *logo_entry = NULL;
+	void *logo_buffer;
 
-	params->LogoSize = cbfs_boot_load_file("logo.bmp", (void *)params->LogoPtr,
+	logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, 1 * MiB);
-					       params->LogoSize, CBFS_TYPE_RAW);
+	if (logo_entry) {
-	if (!params->LogoSize)
+		logo_buffer = cbmem_entry_start(logo_entry);
-		params->LogoPtr = 0;
+		if (logo_buffer) {
+			*logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer,
+							1 * MiB, CBFS_TYPE_RAW);
+			if (logo_size)
+				*logo_ptr = (UINT32)logo_buffer;
+		}
+	}
+	return (logo_entry);
 }

src/drivers/intel/fsp2_0/silicon_init.c

@@ -34,7 +34,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	fsp_silicon_init_fn silicon_init;
 	uint32_t status;
 	uint8_t postcode;
-	const struct cbmem_entry *logo_entry;
+	const struct cbmem_entry *logo_entry = NULL;
 
 	supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
 
@@ -57,14 +57,9 @@ static void do_silicon_init(struct fsp_header *hdr)
 	/* Give SoC/mainboard a chance to populate entries */
 	platform_fsp_silicon_init_params_cb(upd);
 
-#if (CONFIG(HAVE_FSP_GOP))
+	/* Populate logo related entries */
-	if (CONFIG(FSP2_0_DISPLAY_LOGO)) {
+	if (CONFIG(FSP2_0_DISPLAY_LOGO))
-		upd->FspsConfig.LogoSize = 1 * MiB;
+		logo_entry = soc_load_logo(upd);
-		logo_entry = cbmem_entry_add(CBMEM_ID_FSP_LOGO, upd->FspsConfig.LogoSize);
-		upd->FspsConfig.LogoPtr = (UINT32)cbmem_entry_start(logo_entry);
-		load_logo(upd);
-	}
-#endif
 
 	/* Call SiliconInit */
 	silicon_init = (void *) (hdr->image_base +
@@ -77,7 +72,7 @@ static void do_silicon_init(struct fsp_header *hdr)
 	timestamp_add_now(TS_FSP_SILICON_INIT_END);
 	post_code(POST_FSP_SILICON_EXIT);
 
-	if (CONFIG(FSP2_0_DISPLAY_LOGO))
+	if (logo_entry)
 		cbmem_entry_remove(logo_entry);
 
 	fsp_debug_after_silicon_init(status);
@@ -160,3 +155,9 @@ void fsp_silicon_init(bool s3wake)
 	fsps_load(s3wake);
 	do_silicon_init(&fsps_hdr);
 }
+
+/* Load bmp and set FSP parameters, fsp_load_logo can be used */
+__weak const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+{
+	return NULL;
+}

src/soc/intel/apollolake/Kconfig

@@ -102,6 +102,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_CF9_RESET_PREPARE
 	select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
 	select HAVE_FSP_GOP
+	select HAVE_FSP_LOGO_SUPPORT
 	select NO_UART_ON_SUPERIO
 	select INTEL_GMA_ACPI
 	select INTEL_GMA_SWSMISCI

src/soc/intel/apollolake/chip.c

@@ -879,4 +879,10 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
 
+/* Handle FSP logo params */
+const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+{
+	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+}
+
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);

src/soc/intel/cannonlake/Kconfig

@@ -66,6 +66,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_M_XIP
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
+	select HAVE_FSP_LOGO_SUPPORT
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE

src/soc/intel/cannonlake/fsp_params.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -483,3 +484,9 @@ const pci_devfn_t *soc_lpss_controllers_list(size_t *size)
 	*size = ARRAY_SIZE(serial_io_dev);
 	return serial_io_dev;
 }
+
+/* Handle FSP logo params */
+const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+{
+	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+}

src/soc/intel/skylake/Kconfig

@@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_M_XIP
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
+	select HAVE_FSP_LOGO_SUPPORT
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select INTEL_CAR_NEM_ENHANCED

src/soc/intel/skylake/chip.c

@@ -15,6 +15,7 @@
 
 #include <bootmode.h>
 #include <bootstate.h>
+#include <cbmem.h>
 #include <fsp/api.h>
 #include <arch/acpi.h>
 #include <console/console.h>
@@ -416,3 +417,9 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }
+
+/* Handle FSP logo params */
+const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd)
+{
+	return fsp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
+}