From d145c95208b5129701a6a4125767fa0118083cf5 Mon Sep 17 00:00:00 2001
From: Lijian Zhao <lijian.zhao@intel.com>
Date: Mon, 27 Aug 2018 11:14:23 -0700
Subject: [PATCH] soc/intel/cannonlake: Fix comment errors for SMBUS

On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.

BUG=N/A
TEST=N/A

Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
---
 src/soc/intel/cannonlake/acpi/southbridge.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 4a62485324..e4f29b6a37 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -37,7 +37,7 @@
 /* Serial IO */
 #include "serialio.asl"
 
-/* SMBus 0:1f.3 */
+/* SMBus 0:1f.4 */
 #include "smbus.asl"
 
 /* USB XHCI 0:14.0 */