riscv-spike: Replace custom UART with a memory-mapped 8250

Since the HTIF is a non-standard interface, and coreboot already has a
8250 driver, I started implementing an 8250 core for spike[1].

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/mainboard/emulation/spike-riscv/Kconfig

@@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_UCB_RISCV
 	select BOARD_ROMSIZE_KB_4096
 	select ARCH_BOOTBLOCK_RISCV
-	select HAVE_UART_SPECIAL
+	select DRIVERS_UART_8250MEM
 
 config MAINBOARD_DIR
 	string

src/mainboard/emulation/spike-riscv/uart.c

@@ -19,39 +19,7 @@
 #include <boot/coreboot_tables.h>
 #include <spike_util.h>
 
-static uint8_t *buf = (void *)0x3f8;
 uintptr_t uart_platform_base(int idx)
 {
-	return (uintptr_t) buf;
+	return (uintptr_t) 0x40001000;
 }
-
-void uart_init(int idx)
-{
-}
-
-unsigned char uart_rx_byte(int idx)
-{
-	return *buf; // this does not work on spike, requires more implementation details
-}
-
-void uart_tx_byte(int idx, unsigned char data)
-{
-	mcall_console_putchar(data);
-}
-
-void uart_tx_flush(int idx)
-{
-}
-
-#ifndef __PRE_RAM__
-void uart_fill_lb(void *data)
-{
-	struct lb_serial serial;
-	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial.baseaddr = 0x3f8;
-	serial.baud = 115200;
-	serial.regwidth = 1;
-	lb_add_serial(&serial, data);
-        lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
-}
-#endif