diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c
index a324fa3454..df0930c42f 100644
--- a/src/mainboard/google/brya/variants/primus/gpio.c
+++ b/src/mainboard/google/brya/variants/primus/gpio.c
@@ -78,6 +78,8 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
 	/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
 	/* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
 	/* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
@@ -117,16 +119,13 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
 	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
-	/* B4  : PROC_GP3 ==> SSD_PERST_L
-	 * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the
-	 * power rails take some time to come up.
-	 */
-	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 };
 
 static const struct pad_config romstage_gpio_table[] = {
 	/* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_A12, 1, DEEP),
+	/* B4  : PROC_GP3 ==> SSD_PERST_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
 	/* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 };