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Leave power control registers unlocked 

To allow easy experimentation with thermals, leave power control
registers unlocked.

Change-Id: Ia53065f3f220c2faed58e7d53e60c3f169ae58ec
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/1688
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Sameer Nanda 2012-07-25 16:11:40 -07:00 committed by Stefan Reinauer
parent b578627f51
commit d16d576524
1 changed files with 13 additions and 0 deletions
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13
src/cpu/intel/model_206ax/finalize.c
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@ -49,11 +49,24 @@ void intel_model_206ax_finalize_smm(void)
if (cpuid_ecx(1) & (1 << 25)) if (cpuid_ecx(1) & (1 << 25))
msr_set_bit(MSR_FEATURE_CONFIG, 0); msr_set_bit(MSR_FEATURE_CONFIG, 0);
#ifdef LOCK_POWER_CONTROL_REGISTERS
/*
* Lock the power control registers.
*
* These registers can be left unlocked if modifying power
* limits from the OS is desirable. Modifying power limits
* from the OS can be especially useful for experimentation
* during early phases of system bringup while the thermal
* power envelope is being proven.
*/
msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
msr_set_bit(MSR_PKG_POWER_LIMIT, 63); msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
msr_set_bit(MSR_PP0_POWER_LIMIT, 31); msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
msr_set_bit(MSR_PP1_POWER_LIMIT, 31); msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
#endif
msr_set_bit(MSR_MISC_PWR_MGMT, 22); msr_set_bit(MSR_MISC_PWR_MGMT, 22);
msr_set_bit(MSR_LT_LOCK_MEMORY, 0); msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
} }