amd/sr5650: Update add_ivrs_device_entries
Functionally, this should be roughly the same. The only real difference should be removing the 4 bytes of padding from the end of the 4 byte entries. The spec mentions a boundary for the 4 byte entries (which we are ignoring), but doesn't mention a boundary for the 8 byte entries, and I can't think of any other reason that the padding might be needed. - Wrap long lines. - Combine if statements to clean up indentation. - Use #defines from acpi_ivrs.h to make commands easier to understand. - Remove padding from 4 byte entries that made them 8 bytes in length. - Set the pointer p at init, and clear the value at p if the device we're looking at is enabled instead of setting p in every if statement. - Look at the command type to update current and length. - Treat malloc & free as if they were typical instead of coreboot specific versions. Check to make sure the malloc worked and only free on the last loop instead of every time. Change-Id: I79dd5f9e930fad22a09d1af78f33c1d9a88b3bfe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16532 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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Martin Roth
parent
b599919495
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d173907747
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@ -16,6 +16,7 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/acpi_ivrs.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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@ -715,100 +716,91 @@ void sr5650_enable(device_t dev)
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}
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}
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static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length)
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static void add_ivrs_device_entries(struct device *parent, struct device *dev,
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int depth, int linknum, int8_t *root_level,
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unsigned long *current, uint16_t *length)
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{
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uint8_t *p;
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uint8_t *p = (uint8_t *) *current;
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struct device *sibling;
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struct bus *link;
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if (!root_level) {
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root_level = malloc(sizeof(int8_t));
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if (root_level == NULL)
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die("Error: Could not allocate a byte!\n");
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*root_level = -1;
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}
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if (dev->path.type == DEVICE_PATH_PCI) {
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if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0))
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*root_level = depth;
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if ((dev->path.type == DEVICE_PATH_PCI) &&
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(dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0))
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*root_level = depth;
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if (*root_level != -1) {
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if (depth >= *root_level) {
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if (dev->enabled) {
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if (depth == *root_level) {
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if (dev->path.pci.devfn < (0x1 << 3)) {
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/* SR5690 control device */
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} else if ((dev->path.pci.devfn >= (0x1 << 3)) && (dev->path.pci.devfn < (0xe << 3))) {
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/* SR5690 PCIe bridge device */
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} else {
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if (dev->path.pci.devfn == (0x14 << 3)) {
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/* SMBUS controller */
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p = (uint8_t *) *current;
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p[0] = 0x2; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x97; /* Data */
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p[4] = 0x0; /* Padding */
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p[5] = 0x0; /* Padding */
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p[6] = 0x0; /* Padding */
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p[7] = 0x0; /* Padding */
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*length += 8;
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*current += 8;
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} else {
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/* Other southbridge device */
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p = (uint8_t *) *current;
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p[0] = 0x2; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = 0x0; /* Padding */
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p[5] = 0x0; /* Padding */
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p[6] = 0x0; /* Padding */
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p[7] = 0x0; /* Padding */
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*length += 8;
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*current += 8;
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}
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}
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} else {
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if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
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/* Device behind bridge */
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if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {
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/* Device is PCIe */
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p = (uint8_t *) *current;
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p[0] = 0x2; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = 0x0; /* Padding */
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p[5] = 0x0; /* Padding */
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p[6] = 0x0; /* Padding */
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p[7] = 0x0; /* Padding */
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*length += 8;
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*current += 8;
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} else {
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/* Device is legacy PCI or PCI-X */
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p = (uint8_t *) *current;
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p[0] = 0x42; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = 0x0; /* Reserved */
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p[5] = parent->path.pci.devfn; /* Device */
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p[6] = parent->bus->secondary; /* Bus */
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p[7] = 0x0; /* Reserved */
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*length += 8;
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*current += 8;
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}
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}
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}
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}
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if ((dev->path.type == DEVICE_PATH_PCI) && (*root_level != -1) &&
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(depth >= *root_level) && (dev->enabled)) {
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*p = 0;
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if (depth == *root_level) {
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if (dev->path.pci.devfn < (0x1 << 3)) {
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/* SR5690 control device */
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} else if ((dev->path.pci.devfn >= (0x1 << 3)) &&
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(dev->path.pci.devfn < (0xe << 3))) {
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/* SR5690 PCIe bridge device */
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} else if (dev->path.pci.devfn == (0x14 << 3)) {
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/* SMBUS controller */
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p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = IVHD_DTE_LINT_1_PASS | /* Data */
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IVHD_DTE_SYS_MGT_NO_TRANS |
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IVHD_DTE_NMI_PASS |
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IVHD_DTE_EXT_INT_PASS |
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IVHD_DTE_INIT_PASS;
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} else {
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/* Other southbridge device */
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p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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}
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} else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
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/* Device behind bridge */
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if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {
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/* Device is PCIe */
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p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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} else {
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/* Device is legacy PCI or PCI-X */
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p[0] = IVHD_DEV_8_BYTE_ALIAS_SELECT; /* Entry */
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p[1] = dev->path.pci.devfn; /* Device */
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p[2] = dev->bus->secondary; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = 0x0; /* Reserved */
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p[5] = parent->path.pci.devfn; /* Device */
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p[6] = parent->bus->secondary; /* Bus */
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p[7] = 0x0; /* Reserved */
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}
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}
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if (*p == IVHD_DEV_4_BYTE_SELECT) {
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*length += 4;
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*current += 4;
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} else if (*p == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
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*length += 8;
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*current += 8;
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}
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}
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for (link = dev->link_list; link; link = link->next)
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for (sibling = link->children; sibling; sibling = sibling->sibling)
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add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length);
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for (sibling = link->children; sibling;
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sibling = sibling->sibling)
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add_ivrs_device_entries(dev, sibling, depth + 1,
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depth, root_level, current, length);
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free(root_level);
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if (depth == 0)
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free(root_level);
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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