google/kahlee: Enable IOMMU device

Enable the IOMMU device on all kahlee based mainboards.

BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.

Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/28754
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marc Jones 2018-09-26 10:28:30 -06:00 committed by Martin Roth
parent bc94aeaac8
commit d17c4cbf29
4 changed files with 4 additions and 0 deletions

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@ -55,6 +55,7 @@ chip soc/amd/stoneyridge
end end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

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@ -58,6 +58,7 @@ chip soc/amd/stoneyridge
end end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

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@ -58,6 +58,7 @@ chip soc/amd/stoneyridge
end end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge

View File

@ -55,6 +55,7 @@ chip soc/amd/stoneyridge
end end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4
device pci 1.1 on end # Internal Multimedia device pci 1.1 on end # Internal Multimedia
device pci 2.0 on end # PCIe Host Bridge device pci 2.0 on end # PCIe Host Bridge