soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL

Systemagent common code will use MCH_BASE_ADDRESS macro,
hence cleaning current APL code to adhere such changes.

Change-Id: Iace1cf786b08221c3955101186509ac5161c3841
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/acpi/pmc_ipc.asl

@@ -47,9 +47,9 @@ scope (\_SB) {
 			Store (PMC_BAR0, IBAS)
 
 			CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
-			Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA)
+			Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
 			CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
-			Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA)
+			Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
 
 			CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
 			Store (PMC_SRAM_BASE_0, SBAS)

src/soc/intel/apollolake/chip.c

@@ -273,7 +273,8 @@ static void set_power_limits(void)
 				100 * (pl2_val % power_unit) / power_unit);
 
 	/* Get the MMIO address */
-	rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL);
+	rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS +
+				MCHBAR_RAPL_PPL);
 
 	/* Setting RAPL MMIO register for Power limits.
 	* RAPL driver is using MSR instead of MMIO.

src/soc/intel/apollolake/include/soc/iomap.h

@@ -22,15 +22,9 @@
 
 #define P2SB_BAR			CONFIG_PCR_BASE_ADDRESS
 #define P2SB_SIZE			(16 * MiB)
-#define MCH_BASE_ADDR			0xfed10000
+#define MCH_BASE_ADDRESS		0xfed10000
 #define MCH_BASE_SIZE			(32 * KiB)
 
-#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR	0x7168
-#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR	0x7078
-#define PUNIT_THERMAL_DEVICE_IRQ		0x700C
-#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER	0x18
-#define PUINT_THERMAL_DEVICE_IRQ_LOCK		0x80000000
-
 #define ACPI_PMIO_BASE			0x400
 #define ACPI_PMIO_SIZE			0x100
 #define R_ACPI_PM1_TMR			0x8

src/soc/intel/apollolake/include/soc/systemagent.h

@@ -27,6 +27,11 @@
 #define MCH_NUM_IMRS		20
 
 /* RAPL Package Power Limit register under MCHBAR. */
+#define PUNIT_THERMAL_DEVICE_IRQ		0x700C
+#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER	0x18
+#define PUINT_THERMAL_DEVICE_IRQ_LOCK		0x80000000
+#define BIOS_RESET_CPL		0x7078
 #define MCHBAR_RAPL_PPL		0x70A8
+#define CORE_DISABLE_MASK	0x7168
 
 #endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */

src/soc/intel/apollolake/romstage.c

@@ -81,7 +81,7 @@ static uint32_t fsp_version CAR_GLOBAL;
 static void soc_early_romstage_init(void)
 {
 	/* Set MCH base address and enable bit */
-	pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
+	pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1);
 
 	/* Enable decoding for HPET. Needed for FSP global pointer storage */
 	pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
@@ -140,11 +140,10 @@ static bool punit_init(void)
 	 * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
 	 * Enable all cores here.
 	 */
-	write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR),
-		0x0);
+	write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), 0x0);
+
+	void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + BIOS_RESET_CPL);
 
-	void *bios_rest_cpl = (void *)(MCH_BASE_ADDR +
-				       P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR);
 	/* P-Unit bring up */
 	reg = read32(bios_rest_cpl);
 	if (reg == 0xffffffff) {
@@ -156,14 +155,14 @@ static bool punit_init(void)
 	pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
 
 	/* Set PUINT IRQ to 24 and INTPIN LOCK */
-	write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ),
+	write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ),
 		PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
 		PUINT_THERMAL_DEVICE_IRQ_LOCK);
 
-	data = read32((void *)(MCH_BASE_ADDR + 0x7818));
+	data = read32((void *)(MCH_BASE_ADDRESS + 0x7818));
 	data &= 0xFFFFE01F;
 	data |= 0x20 | 0x200;
-	write32((void *)(MCH_BASE_ADDR + 0x7818), data);
+	write32((void *)(MCH_BASE_ADDRESS + 0x7818), data);
 
 	/* Stage0 BIOS Reset Complete (RST_CPL) */
 	write32(bios_rest_cpl, 0x1);