usbdebug: Consolidate EHCI_BAR setup

There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.

Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2017-07-30 11:37:14 +03:00
parent ab1d2ac626
commit d1a0c57708
12 changed files with 8 additions and 55 deletions

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@ -47,12 +47,18 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
u32 cap = pci_read_config32(dev, pos); u32 cap = pci_read_config32(dev, pos);
/* FIXME: We should remove static EHCI_BAR_INDEX. */ /* FIXME: We should remove static EHCI_BAR_INDEX. */
u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1); u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
if (dbg_bar != EHCI_BAR_INDEX) if (ehci_bar != EHCI_BAR_INDEX)
return -1; return -1;
pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
*base = CONFIG_EHCI_BAR; *base = CONFIG_EHCI_BAR;
*dbg_offset = (cap>>16) & 0x1ffc; *dbg_offset = (cap>>16) & 0x1ffc;
return 0; return 0;
} }

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@ -53,8 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */ /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX); outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA); outb(0x7F, PM_DATA);
pci_write_config32(dev, EHCI_BAR_INDEX, base);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER);
} }

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@ -41,12 +41,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
if (!dev)
return;
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */ /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX); outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA); outb(0x7F, PM_DATA);
pci_write_config32(dev, EHCI_BAR_INDEX, base);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
} }

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@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */ /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX); outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA); outb(0x7F, PM_DATA);
pci_write_config32(dev, EHCI_BAR_INDEX, base);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
} }

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@ -35,9 +35,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -48,10 +48,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable all of the USB controllers */ /* Enable all of the USB controllers */
outb(0xEF, PM_INDEX); outb(0xEF, PM_INDEX);
outb(0x7F, PM_DATA); outb(0x7F, PM_DATA);
pci_write_config32(dev, EHCI_BAR_INDEX, base);
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
} }

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@ -63,10 +63,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Bail out. No console to complain in. */ /* Bail out. No console to complain in. */
if (!dev) if (!dev)
return; return;
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }

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@ -46,9 +46,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{ {
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
} }