usbdebug: Consolidate EHCI_BAR setup

There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.

Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/drivers/usb/pci_ehci.c

@@ -47,12 +47,18 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
 	u32 cap = pci_read_config32(dev, pos);
 
 	/* FIXME: We should remove static EHCI_BAR_INDEX. */
-	u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1);
+	u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
-	if (dbg_bar != EHCI_BAR_INDEX)
+	if (ehci_bar != EHCI_BAR_INDEX)
 		return -1;
 
+	pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
+
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+		PCI_COMMAND_MASTER);
+
 	*base = CONFIG_EHCI_BAR;
 	*dbg_offset = (cap>>16) & 0x1ffc;
+
 	return 0;
 }
 

src/soc/amd/stoneyridge/enable_usbdebug.c

@@ -53,8 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
-
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY
-						| PCI_COMMAND_MASTER);
 }

src/soc/intel/broadwell/usb_debug.c

@@ -41,12 +41,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	if (!dev)
-		return;
-
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }

src/southbridge/amd/agesa/hudson/enable_usbdebug.c

@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
-
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }

src/southbridge/amd/pi/hudson/enable_usbdebug.c

@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
-
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }

src/southbridge/amd/sb600/enable_usbdebug.c

@@ -35,9 +35,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }

src/southbridge/amd/sb700/enable_usbdebug.c

@@ -48,10 +48,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
 }

src/southbridge/amd/sb800/enable_usbdebug.c

@@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 	/* Enable all of the USB controllers */
 	outb(0xEF, PM_INDEX);
 	outb(0x7F, PM_DATA);
-
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }

src/southbridge/intel/common/usb_debug.c

@@ -63,10 +63,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 	/* Bail out. No console to complain in. */
 	if (!dev)
 		return;
-
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }

src/southbridge/nvidia/ck804/enable_usbdebug.c

@@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }

src/southbridge/nvidia/mcp55/enable_usbdebug.c

@@ -44,9 +44,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }

src/southbridge/sis/sis966/enable_usbdebug.c

@@ -46,9 +46,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 
 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
 {
-	/* Set the EHCI BAR address. */
-	pci_write_config32(dev, EHCI_BAR_INDEX, base);
-
-	/* Enable access to the EHCI memory space registers. */
-	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 }