diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 369bae3c11..d105b0cfd6 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <arch/cache.h>
+#include <arch/cpu.h>
 #include <arch/lib_helpers.h>
 #include <cpu/cpu.h>
 #include <console/console.h>
@@ -27,6 +28,11 @@
 #include <timer.h>
 #include "cpu-internal.h"
 
+void __attribute__((weak)) arm64_arch_timer_init(void)
+{
+	/* Default weak implementation does nothing. */
+}
+
 static inline void cpu_disable_dev(device_t dev)
 {
 	dev->enabled = 0;
@@ -136,6 +142,9 @@ static void init_this_cpu(void *arg)
 	 * TTA [28] = 0, disable traps for trace register access from EL0/EL1.
 	 */
 	raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
+
+	/* Arch Timer init: setup cntfrq per CPU */
+	arm64_arch_timer_init();
 }
 
 /* Fill in cpu_info structures according to device tree. */
diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h
index 34220d9792..14635e39c0 100644
--- a/src/arch/arm64/include/armv8/arch/cpu.h
+++ b/src/arch/arm64/include/armv8/arch/cpu.h
@@ -181,4 +181,10 @@ void arm64_cpu_startup(void);
  */
 void arm64_cpu_startup_resume(void);
 
+/*
+ * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of
+ * ARM arch timer.
+ */
+void arm64_arch_timer_init(void);
+
 #endif /* __ARCH_CPU_H__ */