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amd/stoneyridge: Rename GppClkCntrl fields 

Make the field names of the MISCx00 GPPClkCntrl more manageable by
shortening their names.  Make the definitions look more like the
rest of the header file.

Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Marshall Dawson 2018-10-05 18:45:15 -06:00 committed by Martin Roth
parent bba0439d09
commit d1aa8eba72
2 changed files with 12 additions and 12 deletions
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12
src/mainboard/google/kahlee/mainboard.c
View File

@ -146,15 +146,15 @@ static void mainboard_init(void *chip_info)
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
GPP_CLK2_CLOCK_REQ_MAP_MASK,
GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
GPP_CLK2_REQ_MAP_MASK,
GPP_CLK2_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_REQ_MAP_SHIFT);
/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
GPP_CLK0_CLOCK_REQ_MAP_MASK,
GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_CLOCK_REQ_MAP_SHIFT);
GPP_CLK0_REQ_MAP_MASK,
GPP_CLK0_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_REQ_MAP_SHIFT);
}
/*************************************************

12
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -111,13 +111,13 @@
/* FCH MISC Registers 0xfed80e00 */
#define GPP_CLK_CNTRL 0
#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
#define GPP_CLK2_REQ_MAP_SHIFT 8
#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT)
#define GPP_CLK2_REQ_MAP_CLK_REQ2 3
#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0
#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT)
#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1
#define GPP_CLK0_REQ_MAP_SHIFT 0
#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT)
#define GPP_CLK0_REQ_MAP_CLK_REQ0 1
#define MISC_CGPLL_CONFIG1 0x08
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)