sb/amd/sp5100: Enable CPU reset timing option per RPR v3.02
Change-Id: Ifb568ca126283e533232f52175d6147ee500220c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14307 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
parent
796e77ef25
commit
d1b6ff80c0
|
@ -677,6 +677,11 @@ static void sb700_pmio_por_init(void)
|
||||||
pmio_write(0xbb, byte);
|
pmio_write(0xbb, byte);
|
||||||
|
|
||||||
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
|
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
|
||||||
|
/* RPR 2.26 Alter CPU reset timing */
|
||||||
|
byte = pmio_read(0xb2);
|
||||||
|
byte |= 0x1 << 2; /* Enable CPU reset timing option */
|
||||||
|
pmio_write(0xb2, byte);
|
||||||
|
|
||||||
/* Work around system clock drift issues */
|
/* Work around system clock drift issues */
|
||||||
byte = pmio_read(0xd4);
|
byte = pmio_read(0xd4);
|
||||||
byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */
|
byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */
|
||||||
|
|
Loading…
Reference in New Issue