nb/intel/x4x: Define and use `HOST_BRIDGE` macro
Other Intel northbridges do this. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
parent
4bc8dfb820
commit
d1c590a666
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@ -13,5 +13,5 @@ void bootblock_early_northbridge_init(void)
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reg32 = TPM32(0);
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reg32 = CONFIG_MMCONF_BASE_ADDRESS | 16 | 1;
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pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
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pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
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}
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@ -15,32 +15,30 @@
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void x4x_early_init(void)
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{
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const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
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/* Setup MCHBAR. */
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pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
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pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
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/* Setup DMIBAR. */
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pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
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pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
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/* Setup EPBAR. */
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pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
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pci_write_config32(HOST_BRIDGE, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
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/* Setup HECIBAR */
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pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8(d0f0, D0F0_PAM(0), 0x30);
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pci_write_config8(d0f0, D0F0_PAM(1), 0x33);
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pci_write_config8(d0f0, D0F0_PAM(2), 0x33);
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pci_write_config8(d0f0, D0F0_PAM(3), 0x33);
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pci_write_config8(d0f0, D0F0_PAM(4), 0x33);
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pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
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pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(0), 0x30);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(1), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(2), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(3), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(4), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(5), 0x33);
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pci_write_config8(HOST_BRIDGE, D0F0_PAM(6), 0x33);
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if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
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if (!(pci_read_config32(HOST_BRIDGE, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
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/* Enable internal GFX */
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pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);
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pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, BOARD_DEVEN);
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/* Set preallocated IGD size from CMOS */
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u8 gfxsize = 6; /* 6 for 64MiB, default if not set in CMOS */
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@ -51,10 +49,10 @@ void x4x_early_init(void)
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else if (gfxsize < 1)
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gfxsize = 1;
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/* Set GTT size to 2+2M */
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pci_write_config16(d0f0, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4);
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pci_write_config16(HOST_BRIDGE, D0F0_GGC, 0x0b00 | (gfxsize + 1) << 4);
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} else { /* Does not feature internal graphics */
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pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
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pci_write_config16(d0f0, D0F0_GGC, (1 << 1));
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pci_write_config32(HOST_BRIDGE, D0F0_DEVEN, D0EN | D1EN | PEG1EN);
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pci_write_config16(HOST_BRIDGE, D0F0_GGC, (1 << 1));
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}
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}
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@ -72,7 +72,7 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
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{0, 0},
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};
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const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO);
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const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO);
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if (!(pciexbar_reg & 1)) {
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printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
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@ -95,13 +95,13 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
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static size_t northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
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const u8 esmramc = pci_read_config8(HOST_BRIDGE, D0F0_ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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static uintptr_t northbridge_get_tseg_base(void)
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{
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return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
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return pci_read_config32(HOST_BRIDGE, D0F0_TSEG);
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}
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@ -122,11 +122,11 @@ static void mchinfo_ddr2(struct sysinfo *s)
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const u32 eax = cpuid_ext(0x04, 0).eax;
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printk(BIOS_WARNING, "%d CPU cores\n", ((eax >> 26) & 0x3f) + 1);
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u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), 0xe8);
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u32 capid = pci_read_config16(HOST_BRIDGE, 0xe8);
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if (!(capid & (1<<(79-64))))
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printk(BIOS_WARNING, "iTPM enabled\n");
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capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
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capid = pci_read_config32(HOST_BRIDGE, 0xe4);
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if (!(capid & (1<<(57-32))))
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printk(BIOS_WARNING, "ME enabled\n");
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@ -246,7 +246,7 @@ static void select_cas_dramfreq_ddr3(struct sysinfo *s,
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u32 min_tCLK;
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u8 try_CAS;
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u16 capid = (pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f;
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u16 capid = (pci_read_config16(HOST_BRIDGE, 0xea) >> 4) & 0x3f;
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switch (s->max_fsb) {
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default:
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@ -344,7 +344,7 @@ static void workaround_stacked_mode(struct sysinfo *s)
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if (s->selected_timings.mem_clk != MEM_CLOCK_1066MHz)
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return;
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/* IGD0EN gets disabled if not present before this code runs */
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deven = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN);
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deven = pci_read_config32(HOST_BRIDGE, D0F0_DEVEN);
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if (deven & IGD0EN)
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s->stacked_mode = 1;
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}
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@ -593,9 +593,9 @@ static void checkreset_ddr2(int boot_path)
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
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/* do magic 0xf0 thing. */
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pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
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pci_and_config8(HOST_BRIDGE, 0xf0, ~(1 << 2));
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pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
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pci_or_config8(HOST_BRIDGE, 0xf0, (1 << 2));
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full_reset();
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}
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@ -616,7 +616,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "Setting up RAM controller.\n");
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pci_write_config8(PCI_DEV(0, 0, 0), 0xdf, 0xff);
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pci_write_config8(HOST_BRIDGE, 0xdf, 0xff);
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memset(&s, 0, sizeof(struct sysinfo));
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@ -671,7 +671,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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checkreset_ddr2(s.boot_path);
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/* Detect dimms per channel */
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xe9);
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reg8 = pci_read_config8(HOST_BRIDGE, 0xe9);
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printk(BIOS_DEBUG, "Dimms per channel: %d\n",
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(reg8 & 0x10) ? 1 : 2);
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@ -687,7 +687,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
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pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1);
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pci_or_config8(HOST_BRIDGE, 0xf4, 1);
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printk(BIOS_DEBUG, "RAM initialization finished.\n");
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@ -1270,14 +1270,14 @@ static void pre_jedec_memory_map(void)
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MCHBAR8(0x110) = (2 << 5) | (3 << 3);
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MCHBAR16(0x10e) = 0;
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MCHBAR32(0x108) = 0;
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000);
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pci_write_config16(HOST_BRIDGE, D0F0_TOLUD, 0x4000);
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/* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10);
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pci_write_config16(HOST_BRIDGE, D0F0_TOM, 0x10);
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/* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */
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pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000);
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pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000);
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pci_write_config16(HOST_BRIDGE, D0F0_TOUUD, 0x0400);
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pci_write_config32(HOST_BRIDGE, D0F0_GBSM, 0x40000000);
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pci_write_config32(HOST_BRIDGE, D0F0_BGSM, 0x40000000);
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pci_write_config32(HOST_BRIDGE, D0F0_TSEG, 0x40000000);
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}
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u32 test_address(int channel, int rank)
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@ -1702,7 +1702,7 @@ static void configure_mmap(struct sysinfo *s)
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160, 224, 352 };
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u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
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ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
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ggc = pci_read_config16(HOST_BRIDGE, 0x52);
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gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
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gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
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/* TSEG 2M, This amount can easily be covered by SMRR MTRR's,
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@ -1733,20 +1733,20 @@ static void configure_mmap(struct sysinfo *s)
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gttbase = gfxbase - gttsize;
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tsegbase = gttbase - tsegsize;
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pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4);
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pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6);
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pci_write_config16(HOST_BRIDGE, 0xb0, tolud << 4);
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pci_write_config16(HOST_BRIDGE, 0xa0, tom >> 6);
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if (reclaim) {
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pci_write_config16(PCI_DEV(0, 0, 0), 0x98,
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pci_write_config16(HOST_BRIDGE, 0x98,
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(u16)(reclaimbase >> 6));
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pci_write_config16(PCI_DEV(0, 0, 0), 0x9a,
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pci_write_config16(HOST_BRIDGE, 0x9a,
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(u16)(reclaimlimit >> 6));
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}
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pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
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pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
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pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
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pci_write_config16(HOST_BRIDGE, 0xa2, touud);
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pci_write_config32(HOST_BRIDGE, 0xa4, gfxbase << 20);
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pci_write_config32(HOST_BRIDGE, 0xa8, gttbase << 20);
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/* Enable and set TSEG size to 2M */
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pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
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pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
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pci_update_config8(HOST_BRIDGE, D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
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pci_write_config32(HOST_BRIDGE, 0xac, tsegbase << 20);
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}
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static void set_enhanced_mode(struct sysinfo *s)
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@ -1779,8 +1779,8 @@ static void set_enhanced_mode(struct sysinfo *s)
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MCHBAR32(0x400*ch + 0x290) = 0x4f2091c;
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}
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
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pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1);
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reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
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pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1);
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MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk ==
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FSB_CLOCK_1333MHz ? 0x20000 : 0));
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reg32 = 0x219100c2;
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@ -1822,7 +1822,7 @@ static void set_enhanced_mode(struct sysinfo *s)
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if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)
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reg32 |= 0x20000;
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MCHBAR32(0x20) = reg32;
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pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1);
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pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1);
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}
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static void power_settings(struct sysinfo *s)
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@ -1943,7 +1943,7 @@ static void power_settings(struct sysinfo *s)
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MCHBAR32(0x1110) = 0x10810350 & ~0x78;
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MCHBAR32(0x1114) = 0;
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x592 = 0xff;
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if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3)
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if (pci_read_config8(HOST_BRIDGE, 0x8) < 3)
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x592 = ~0x4;
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FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
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@ -2056,7 +2056,7 @@ void do_raminit(struct sysinfo *s, int fast_boot)
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MCHBAR8_OR(0x5d8, 0x7);
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}
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if (CHANNEL_IS_POPULATED(s->dimms, 1)) {
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if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) {
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if (pci_read_config8(HOST_BRIDGE, 0x8) < 2) {
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MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
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MCHBAR8_OR(0x5d8, 1);
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}
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@ -9,6 +9,8 @@
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/*
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* D0:F0
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*/
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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#include "hostbridge_regs.h"
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/*
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