soc/intel/broadwell: Drop old forked version of SMBUS support
Switch to use the more recent version in sb/intel/common. Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
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select HAVE_SMI_HANDLER
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
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select HAVE_USBDEBUG
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select IOAPIC
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@ -53,8 +53,6 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
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ramstage-y += sata.c
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ramstage-y += serialio.c
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ramstage-y += smbus.c
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ramstage-y += smbus_common.c
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romstage-y += smbus_common.c
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ramstage-y += smi.c
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smm-y += smihandler.c
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ramstage-y += smmrelocate.c
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@ -43,6 +43,5 @@ void pch_uart_init(void);
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void intel_early_me_status(void);
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void enable_smbus(void);
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int smbus_read_byte(unsigned int device, unsigned int address);
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#endif
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@ -40,9 +40,4 @@
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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#define SMBUS_SLAVE_ADDR 0x24
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int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
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unsigned int address);
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int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
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unsigned int address, unsigned int data);
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#endif
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@ -40,8 +40,3 @@ void enable_smbus(void)
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{
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reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
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}
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int smbus_read_byte(unsigned int device, unsigned int address)
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{
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return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
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}
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@ -24,6 +24,7 @@
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#include <soc/iomap.h>
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#include <soc/ramstage.h>
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#include <soc/smbus.h>
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#include <southbridge/intel/common/smbus.h>
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static void pch_smbus_init(struct device *dev)
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{
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@ -1,149 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/smbus_def.h>
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#include <device/pci.h>
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#include <soc/ramstage.h>
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#include <soc/smbus.h>
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static void smbus_delay(void)
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{
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inb(0x80);
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}
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static int smbus_wait_until_ready(u16 smbus_base)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while (byte & 1);
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return loops ? 0 : -1;
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}
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static int smbus_wait_until_done(u16 smbus_base)
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{
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unsigned int loops = SMBUS_TIMEOUT;
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unsigned char byte;
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do {
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smbus_delay();
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if (--loops == 0)
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break;
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byte = inb(smbus_base + SMBHSTSTAT);
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} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
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return loops ? 0 : -1;
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}
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int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
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unsigned int address)
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{
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(0, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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byte = inb(smbus_base + SMBHSTDAT0);
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if (global_status_register != (1 << 1))
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return SMBUS_ERROR;
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return byte;
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}
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int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
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unsigned int address, unsigned int data)
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{
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unsigned char global_status_register;
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if (smbus_wait_until_ready(smbus_base) < 0)
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return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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/* Setup transaction */
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/* Disable interrupts */
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outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
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/* Set the device I'm talking to */
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outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
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/* Set the command/address... */
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outb(address & 0xff, smbus_base + SMBHSTCMD);
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/* Set up for a byte data read */
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outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
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(smbus_base + SMBHSTCTL));
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/* Clear any lingering errors, so the transaction will run */
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outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
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/* Clear the data byte... */
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outb(data, smbus_base + SMBHSTDAT0);
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/* Start the command */
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outb((inb(smbus_base + SMBHSTCTL) | 0x40),
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smbus_base + SMBHSTCTL);
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/* Poll for transaction completion */
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if (smbus_wait_until_done(smbus_base) < 0) {
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printk(BIOS_ERR, "SMBUS transaction timeout\n");
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return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
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}
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global_status_register = inb(smbus_base + SMBHSTSTAT);
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/* Ignore the "In Use" status... */
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global_status_register &= ~(3 << 5);
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/* Read results of transaction */
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if (global_status_register != (1 << 1)) {
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printk(BIOS_ERR, "SMBUS transaction error\n");
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return SMBUS_ERROR;
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}
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return 0;
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}
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