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soc/intel/broadwell: Drop old forked version of SMBUS support 

Switch to use the more recent version in sb/intel/common.

Change-Id: Icbd54b5671ea2a94aea5db4642698ef679540625
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-01-02 18:03:24 +02:00
parent 7ca19b289e
commit d1c69c65ce
7 changed files with 2 additions and 162 deletions
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1
src/soc/intel/broadwell/Kconfig
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@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select HAVE_USBDEBUG select HAVE_USBDEBUG
select IOAPIC select IOAPIC

2
src/soc/intel/broadwell/Makefile.inc
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@ -53,8 +53,6 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
ramstage-y += sata.c ramstage-y += sata.c
ramstage-y += serialio.c ramstage-y += serialio.c
ramstage-y += smbus.c ramstage-y += smbus.c
ramstage-y += smbus_common.c
romstage-y += smbus_common.c
ramstage-y += smi.c ramstage-y += smi.c
smm-y += smihandler.c smm-y += smihandler.c
ramstage-y += smmrelocate.c ramstage-y += smmrelocate.c

1
src/soc/intel/broadwell/include/soc/romstage.h
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@ -43,6 +43,5 @@ void pch_uart_init(void);
void intel_early_me_status(void); void intel_early_me_status(void);
void enable_smbus(void); void enable_smbus(void);
int smbus_read_byte(unsigned int device, unsigned int address);
#endif #endif

5
src/soc/intel/broadwell/include/soc/smbus.h
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@ -40,9 +40,4 @@
#define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_TIMEOUT (10 * 1000 * 100)
#define SMBUS_SLAVE_ADDR 0x24 #define SMBUS_SLAVE_ADDR 0x24
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
unsigned int address);
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data);
#endif #endif

5
src/soc/intel/broadwell/romstage/smbus.c
View File

@ -40,8 +40,3 @@ void enable_smbus(void)
{ {
reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
} }
int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
}

1
src/soc/intel/broadwell/smbus.c
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@ -24,6 +24,7 @@
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include <soc/smbus.h> #include <soc/smbus.h>
#include <southbridge/intel/common/smbus.h>
static void pch_smbus_init(struct device *dev) static void pch_smbus_init(struct device *dev)
{ {

149
src/soc/intel/broadwell/smbus_common.c
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@ -1,149 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <device/smbus_def.h>
#include <device/pci.h>
#include <soc/ramstage.h>
#include <soc/smbus.h>
static void smbus_delay(void)
{
inb(0x80);
}
static int smbus_wait_until_ready(u16 smbus_base)
{
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
if (--loops == 0)
break;
byte = inb(smbus_base + SMBHSTSTAT);
} while (byte & 1);
return loops ? 0 : -1;
}
static int smbus_wait_until_done(u16 smbus_base)
{
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
if (--loops == 0)
break;
byte = inb(smbus_base + SMBHSTSTAT);
} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
return loops ? 0 : -1;
}
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
/* Set the device I'm talking to */
outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
/* Set the command/address... */
outb(address & 0xff, smbus_base + SMBHSTCMD);
/* Set up for a byte data read */
outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
(smbus_base + SMBHSTCTL));
/* Clear any lingering errors, so the transaction will run */
outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
/* Clear the data byte... */
outb(0, smbus_base + SMBHSTDAT0);
/* Start the command */
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
global_status_register = inb(smbus_base + SMBHSTSTAT);
/* Ignore the "In Use" status... */
global_status_register &= ~(3 << 5);
/* Read results of transaction */
byte = inb(smbus_base + SMBHSTDAT0);
if (global_status_register != (1 << 1))
return SMBUS_ERROR;
return byte;
}
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data)
{
unsigned char global_status_register;
if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
/* Set the device I'm talking to */
outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
/* Set the command/address... */
outb(address & 0xff, smbus_base + SMBHSTCMD);
/* Set up for a byte data read */
outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
(smbus_base + SMBHSTCTL));
/* Clear any lingering errors, so the transaction will run */
outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
/* Clear the data byte... */
outb(data, smbus_base + SMBHSTDAT0);
/* Start the command */
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
printk(BIOS_ERR, "SMBUS transaction timeout\n");
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inb(smbus_base + SMBHSTSTAT);
/* Ignore the "In Use" status... */
global_status_register &= ~(3 << 5);
/* Read results of transaction */
if (global_status_register != (1 << 1)) {
printk(BIOS_ERR, "SMBUS transaction error\n");
return SMBUS_ERROR;
}
return 0;
}