soc/intel/skylake: refactor rtc failure checking

In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.

BUG=b:63054105

Change-Id: I88bf9bdba8c1f3a11bc8301869e3da9f033ec381
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21554
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aaron Durbin 2017-09-15 12:37:05 -06:00
parent bcd0bdabed
commit d1fc8c1343
3 changed files with 21 additions and 13 deletions

View File

@ -193,6 +193,9 @@ void pmc_set_disb(void);
/* Initialize GPEs */
void pmc_gpe_init(void);
/* Return non-zero when RTC failure happened. */
int rtc_failure(void);
static inline int deep_s3_enabled(void)
{
uint32_t deep_s3_pol;

View File

@ -107,22 +107,10 @@ static void pch_set_acpi_mode(void)
static void pch_rtc_init(void)
{
u8 reg8;
int rtc_failed;
/*PMC Controller Device 0x1F, Func 02*/
device_t dev = PCH_DEV_PMC;
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_B, reg8);
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
/* Ensure the date is set including century byte. */
cmos_check_update_date();
cmos_init(rtc_failed);
cmos_init(rtc_failure());
}
static void pch_power_options(void)

View File

@ -541,3 +541,20 @@ void pmc_gpe_init(void)
enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
config->gpe0_en_3, config->gpe0_en_4);
}
int rtc_failure(void)
{
u8 reg8;
int rtc_failed;
/* PMC Controller Device 0x1F, Func 02 */
device_t dev = PCH_DEV_PMC;
reg8 = pci_read_config8(dev, GEN_PMCON_B);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_B, reg8);
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
}
return !!rtc_failed;
}