diff --git a/src/mainboard/amd/majolica/Makefile.inc b/src/mainboard/amd/majolica/Makefile.inc
index 3a9f367eee..64f86bde34 100644
--- a/src/mainboard/amd/majolica/Makefile.inc
+++ b/src/mainboard/amd/majolica/Makefile.inc
@@ -3,6 +3,8 @@
 bootblock-y += bootblock.c
 bootblock-y += early_gpio.c
 
+ramstage-y += chromeos.c
+
 APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
 APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin
 
diff --git a/src/mainboard/amd/majolica/chromeos.c b/src/mainboard/amd/majolica/chromeos.c
new file mode 100644
index 0000000000..c73e047933
--- /dev/null
+++ b/src/mainboard/amd/majolica/chromeos.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Majolica doesn't have a write protect pin */
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* No ChromeOS GPIOs */
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c
index b38184076e..1a7be4be29 100644
--- a/src/mainboard/amd/majolica/mainboard.c
+++ b/src/mainboard/amd/majolica/mainboard.c
@@ -7,6 +7,7 @@
 #include <soc/acpi.h>
 #include <string.h>
 #include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /*
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -94,6 +95,8 @@ static void mainboard_enable(struct device *dev)
 	init_tables();
 	/* Initialize the PIRQ data structures for consumption */
 	pirq_setup();
+
+	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {