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tigerlake: update processor power limits configuration 

Update processor power limit configuration parameters based on
common code base support for Intel Tigerlake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on volteer system

Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sumeet R Pawnikar 2020-05-15 15:55:37 +05:30 committed by Patrick Georgi
parent 425d8640fa
commit d2132469ae
4 changed files with 18 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/tigerlake/Kconfig
View File

@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SSE2 select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

7
src/soc/intel/tigerlake/chip.h
View File

@ -7,6 +7,7 @@
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/gpio.h> #include <intelblocks/gpio.h>
#include <intelblocks/gspi.h> #include <intelblocks/gspi.h>
#include <intelblocks/power_limit.h>
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <soc/gpio_defs.h> #include <soc/gpio_defs.h>
@ -26,6 +27,9 @@ struct soc_intel_tigerlake_config {
/* Common struct containing soc config data required by common code */ /* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config; struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */
struct soc_power_limits_config power_limits_config;
/* Gpio group routed to each dword of the GPE0 block. Values are /* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */ * of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
@ -144,8 +148,7 @@ struct soc_intel_tigerlake_config {
/* HeciEnabled decides the state of Heci1 at end of boot /* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */ * Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled; uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* Intel Speed Shift Technology */ /* Intel Speed Shift Technology */
uint8_t speed_shift_enable; uint8_t speed_shift_enable;

3
src/soc/intel/tigerlake/include/soc/cpu.h
View File

@ -24,7 +24,4 @@
/* Common Timer Copy (CTC) frequency - 38.4MHz. */ /* Common Timer Copy (CTC) frequency - 38.4MHz. */
#define CTC_FREQ 38400000 #define CTC_FREQ 38400000
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
#endif #endif

12
src/soc/intel/tigerlake/systemagent.c
View File

@ -7,10 +7,13 @@
*/ */
#include <device/device.h> #include <device/device.h>
#include <delay.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/systemagent.h> #include <intelblocks/systemagent.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h> #include <soc/systemagent.h>
/* /*
@ -60,9 +63,18 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
*/ */
void soc_systemagent_init(struct device *dev) void soc_systemagent_init(struct device *dev)
{ {
struct soc_power_limits_config *soc_config;
config_t *config;
/* Enable Power Aware Interrupt Routing */ /* Enable Power Aware Interrupt Routing */
enable_power_aware_intr(); enable_power_aware_intr();
/* Enable BIOS Reset CPL */ /* Enable BIOS Reset CPL */
enable_bios_reset_cpl(); enable_bios_reset_cpl();
/* Configure turbo power limits 1ms after reset complete bit */
mdelay(1);
config = config_of_soc();
soc_config = &config->power_limits_config;
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
} }