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arm(64): Replace write32() and friends with writel() 

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner 2015-02-19 14:08:04 -08:00 committed by Patrick Georgi
parent 24f9476531
commit d21a329866
43 changed files with 366 additions and 498 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/include/arch/io.h
View File

@ -33,6 +33,8 @@
*/
#define readb(a) read8(a)
#define writeb(v,a) write8(v,a)
#define readw(a) read16(a)
#define writew(v,a) write16(v,a)
#define readl(a) read32(a)
#define writel(v,a) write32(v,a)

12
src/cpu/allwinner/a10/clock.c
View File

@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 |= 1 << (periph & 0x1f);
write32(reg32, addr);
writel(reg32, addr);
}
/**
@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
addr = (void *)A1X_CCM_BASE + (periph >> 5);
reg32 = read32(addr);
reg32 &= ~(1 << (periph & 0x1f));
write32(reg32, addr);
writel(reg32, addr);
}
/**
@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
reg32 |= PLL5_PLL_ENABLE;
write32(reg32, &ccm->pll5_cfg);
writel(reg32, &ccm->pll5_cfg);
}
/**
@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
write32(reg32, &ccm->cpu_ahb_apb0_cfg);
writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
write32(reg32, &ccm->cpu_ahb_apb0_cfg);
writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void spin_delay(u32 loops)
@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
change_sys_divisors(axi, ahb_exp, apb0_exp);
/* Configure PLL1 at the desired frequency */
write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
writel(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
spin_delay(8);
cpu_clk_src_switch(CPU_CLK_SRC_PLL1);

2
src/cpu/allwinner/a10/gpio.c
View File

@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val)
if ((port > GPS))
return;
write32(val, &gpio->port[port].dat);
writel(val, &gpio->port[port].dat);
}
/**

4
src/cpu/allwinner/a10/pinmux.c
View File

@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func)
reg32 = read32(&gpio->port[port].cfg[reg]);
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
write32(reg32, &gpio->port[port].cfg[reg]);
writel(reg32, &gpio->port[port].cfg[reg]);
}
/**
@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func)
reg32 &= ~(0xf << bit);
reg32 |= (pad_func & 0xf) << bit;
}
write32(reg32, &gpio->port[port].cfg[reg]);
writel(reg32, &gpio->port[port].cfg[reg]);
}
}

28
src/cpu/allwinner/a10/raminit.c
View File

@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
u32 i;
for (i = 0; i < 32; i++)
write32(hpcr_value[i], &dram->hpcr[i]);
writel(hpcr_value[i], &dram->hpcr[i]);
}
static void mctl_setup_dram_clock(u32 clk)
@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
tmp_val = tmp_val * 9 - 200;
reg32 |= tmp_val << 8;
reg32 |= 0x8 << 24;
write32(reg32, &dram->drr);
writel(reg32, &dram->drr);
} else {
write32(0x0, &dram->drr);
writel(0x0, &dram->drr);
}
}
@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
a1x_gate_dram_clock_output();
/* select dram controller 1 */
write32(DRAM_CSEL_MAGIC, &dram->csel);
writel(DRAM_CSEL_MAGIC, &dram->csel);
mctl_itm_disable();
mctl_enable_dll0(para->tpr3);
@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
reg32 |= DRAM_DCR_CMD_RANK_ALL;
reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
write32(reg32, &dram->dcr);
writel(reg32, &dram->dcr);
/* dram clock on */
a1x_ungate_dram_clock_output();
@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
reg32 = ((para->zq) >> 8) & 0xfffff;
reg32 |= ((para->zq) & 0xff) << 20;
reg32 |= (para->zq) & 0xf0000000;
write32(reg32, &dram->zqcr0);
writel(reg32, &dram->zqcr0);
/* set I/O configure register */
reg32 = 0x00cc0000;
reg32 |= (para->odt_en) & 0x3;
reg32 |= ((para->odt_en) & 0x3) << 30;
write32(reg32, &dram->iocr);
writel(reg32, &dram->iocr);
/* set refresh period */
dramc_set_autorefresh_cycle(para->clock);
/* set timing parameters */
write32(para->tpr0, &dram->tpr0);
write32(para->tpr1, &dram->tpr1);
write32(para->tpr2, &dram->tpr2);
writel(para->tpr0, &dram->tpr0);
writel(para->tpr1, &dram->tpr1);
writel(para->tpr2, &dram->tpr2);
if (para->type == DRAM_MEMORY_TYPE_DDR3) {
reg32 = DRAM_MR_BURST_LENGTH(0x0);
@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
reg32 |= DRAM_MR_CAS_LAT(para->cas);
reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
}
write32(reg32, &dram->mr);
writel(reg32, &dram->mr);
write32(para->emr1, &dram->emr);
write32(para->emr2, &dram->emr2);
write32(para->emr3, &dram->emr3);
writel(para->emr1, &dram->emr);
writel(para->emr2, &dram->emr2);
writel(para->emr3, &dram->emr3);
/* set DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);

6
src/cpu/allwinner/a10/timer.c
View File

@ -24,13 +24,13 @@ void init_timer(void)
{
u32 reg32;
/* Load the timer rollover value */
write32(0xffffffff, &tmr0->interval);
writel(0xffffffff, &tmr0->interval);
/* Configure the timer to run from 24MHz oscillator, no prescaler */
reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
reg32 |= TIMER_CTRL_RELOAD;
reg32 |= TIMER_CTRL_TMR_EN;
write32(reg32, &tmr0->ctrl);
writel(reg32, &tmr0->ctrl);
}
void udelay(unsigned usec)
@ -61,6 +61,6 @@ void udelay(unsigned usec)
*/
u8 a1x_get_cpu_chip_revision(void)
{
write32(0, &timer_module->cpu_cfg);
writel(0, &timer_module->cpu_cfg);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}

14
src/cpu/allwinner/a10/twi.c
View File

@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
/* Pre-divide the clock by 8 */
n = 3;
m = (apb_clk >> n) / speed_hz;
write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
writel(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
}
void a1x_twi_init(u8 bus, u32 speed_hz)
@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
configure_clock(twi, speed_hz);
/* Enable the I²C bus */
write32(TWI_CTL_BUS_EN, &twi->ctl);
writel(TWI_CTL_BUS_EN, &twi->ctl);
/* Issue soft reset */
write32(1, &twi->reset);
writel(1, &twi->reset);
while (i-- && read32(&twi->reset))
udelay(1);
@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
static void clear_interrupt_flag(struct a1x_twi *twi)
{
write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
writel(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
}
static void i2c_send_data(struct a1x_twi *twi, u8 data)
{
write32(data, &twi->data);
writel(data, &twi->data);
clear_interrupt_flag(twi);
}
@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_START;
write32(reg32, &twi->ctl);
writel(reg32, &twi->ctl);
/* M_START is automatically cleared after condition is transmitted */
i = TWI_TIMEOUT;
@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
reg32 = read32(&twi->ctl);
reg32 &= ~TWI_CTL_INT_FLAG;
reg32 |= TWI_CTL_M_STOP;
write32(reg32, &twi->ctl);
writel(reg32, &twi->ctl);
}
static int i2c_read(struct a1x_twi *twi, uint8_t chip,

12
src/cpu/allwinner/a10/uart.c
View File

@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
div = (u16) uart_baudrate_divisor(baud_rate,
uart_platform_refclk(), 16);
/* Enable access to Divisor Latch register */
write32(UART8250_LCR_DLAB, &uart->lcr);
writel(UART8250_LCR_DLAB, &uart->lcr);
/* Set baudrate */
write32((div >> 8) & 0xff, &uart->dlh);
write32(div & 0xff, &uart->dll);
writel((div >> 8) & 0xff, &uart->dlh);
writel(div & 0xff, &uart->dll);
/* Set line control */
reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
switch (parity) {
@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
default:
break;
}
write32(reg32, &uart->lcr);
writel(reg32, &uart->lcr);
}
static void a10_uart_enable_fifos(struct a10_uart *uart)
{
write32(UART8250_FCR_FIFO_EN, &uart->fcr);
writel(UART8250_FCR_FIFO_EN, &uart->fcr);
}
static int tx_fifo_full(struct a10_uart *uart)
@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
{
while (tx_fifo_full(uart)) ;
return write32(data, &uart->thr);
return writel(data, &uart->thr);
}

52
src/cpu/ti/am335x/uart.c
View File

@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div)
uint16_t lcr_orig, efr_orig, mcr_orig;
/* reset the UART */
write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
writew(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
while (!(read16(&uart->syss) & SYSS_RESETDONE))
;
/* 1. switch to register config mode B */
lcr_orig = read16(&uart->lcr);
write16(0xbf, &uart->lcr);
writew(0xbf, &uart->lcr);
/*
* 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
* be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
*/
efr_orig = read16(&uart->efr);
write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
/* 3. Switch to register config mode A */
write16(0x80, &uart->lcr);
writew(0x80, &uart->lcr);
/* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
mcr_orig = read16(&uart->mcr);
write16(mcr_orig | MCR_TCR_TLR, &uart->mcr);
writew(mcr_orig | MCR_TCR_TLR, &uart->mcr);
/* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
write16(FCR_FIFO_EN, &uart->fcr);
writew(FCR_FIFO_EN, &uart->fcr);
/* 6. Switch to configuration mode B */
write16(0xbf, &uart->lcr);
writew(0xbf, &uart->lcr);
/* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
/* 9. Restore original EFR value */
write16(efr_orig, &uart->efr);
writew(efr_orig, &uart->efr);
/* 10. Switch to config mode A */
write16(0x80, &uart->lcr);
writew(0x80, &uart->lcr);
/* 11. Restore original MCR value */
write16(mcr_orig, &uart->mcr);
writew(mcr_orig, &uart->mcr);
/* 12. Restore original LCR value */
write16(lcr_orig, &uart->lcr);
writew(lcr_orig, &uart->lcr);
/* Protocol, baud rate and interrupt settings */
/* 1. Disable UART access to DLL and DLH registers */
write16(read16(&uart->mdr1) | 0x7, &uart->mdr1);
writew(read16(&uart->mdr1) | 0x7, &uart->mdr1);
/* 2. Switch to config mode B */
write16(0xbf, &uart->lcr);
writew(0xbf, &uart->lcr);
/* 3. Enable access to IER[7:4] */
write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
/* 4. Switch to operational mode */
write16(0x0, &uart->lcr);
writew(0x0, &uart->lcr);
/* 5. Clear IER */
write16(0x0, &uart->ier);
writew(0x0, &uart->ier);
/* 6. Switch to config mode B */
write16(0xbf, &uart->lcr);
writew(0xbf, &uart->lcr);
/* 7. Set dll and dlh to the desired values (table 19-25) */
write16((div >> 8), &uart->dlh);
write16((div & 0xff), &uart->dll);
writew((div >> 8), &uart->dlh);
writew((div & 0xff), &uart->dll);
/* 8. Switch to operational mode to access ier */
write16(0x0, &uart->lcr);
writew(0x0, &uart->lcr);
/* 9. Clear ier to disable all interrupts */
write16(0x0, &uart->ier);
writew(0x0, &uart->ier);
/* 10. Switch to config mode B */
write16(0xbf, &uart->lcr);
writew(0xbf, &uart->lcr);
/* 11. Restore efr */
write16(efr_orig, &uart->efr);
writew(efr_orig, &uart->efr);
/* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
write16(0x3, &uart->lcr);
writew(0x3, &uart->lcr);
/* 13. Load the new UART mode */
write16(0x0, &uart->mdr1);
writew(0x0, &uart->mdr1);
}
/*
@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data)
{
while (!(read16(&uart->lsr) & LSR_TXFIFOE));
return write8(data, &uart->thr);
return writeb(data, &uart->thr);
}
unsigned int uart_platform_refclk(void)

2
src/drivers/gic/gic.c
View File

@ -61,7 +61,7 @@ static struct gic *gic_get(void)
static inline void gic_write(uint32_t *base, uint32_t val)
{
write32(val, base);
writel(val, base);
}
static void gic_write_regs(uint32_t *base, size_t num_regs, uint32_t val)

14
src/mainboard/cubietech/cubieboard/bootblock.c
View File

@ -38,12 +38,12 @@ static void cubieboard_set_sys_clock(void)
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
/* Switch CPU clock to main oscillator */
write32(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
writel(CPU_AHB_APB0_DEFAULT, &ccm->cpu_ahb_apb0_cfg);
/* Configure the PLL1. The value is the same one used by u-boot
* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
*/
write32(0xa1005000, &ccm->pll1_cfg);
writel(0xa1005000, &ccm->pll1_cfg);
/* FIXME: Delay to wait for PLL to lock */
u32 wait = 1000;
@ -53,7 +53,7 @@ static void cubieboard_set_sys_clock(void)
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= CPU_CLK_SRC_PLL1;
write32(reg32, &ccm->cpu_ahb_apb0_cfg);
writel(reg32, &ccm->cpu_ahb_apb0_cfg);
}
static void cubieboard_setup_clocks(void)
@ -62,12 +62,12 @@ static void cubieboard_setup_clocks(void)
cubieboard_set_sys_clock();
/* Configure the clock source for APB1. This drives our UART */
write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
&ccm->apb1_clk_div_cfg);
writel(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0),
&ccm->apb1_clk_div_cfg);
/* Configure the clock for SD0 */
write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0)
| SDx_RAT_M(1), &ccm->sd0_clk_cfg);
writel(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1),
&ccm->sd0_clk_cfg);
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);

4
src/soc/nvidia/tegra/apbmisc.c
View File

@ -26,12 +26,12 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
void enable_jtag(void)
{
write32(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
writel(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
}
void clamp_tristate_inputs(void)
{
write32(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
writel(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
}
void tegra_revision_info(struct tegra_revision *id)

4
src/soc/nvidia/tegra/gpio.c
View File

@ -67,8 +67,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value)
u32 new_reg = (reg & ~mask) | (value & mask);
if (new_reg != reg) {
write32(new_reg, (u8 *)&gpio_banks[bank] + offset +
port * sizeof(u32));
writel(new_reg,
(u8 *)&gpio_banks[bank] + offset + port * sizeof(u32));
}
}

12
src/soc/nvidia/tegra/i2c.c
View File

@ -40,9 +40,9 @@ static void do_bus_clear(int bus)
// 4. Set TERMINATE condition (1 = IMMEDIATE)
bc = read32(&regs->bus_clear_config);
bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
write32(bc, &regs->bus_clear_config);
writel(bc, &regs->bus_clear_config);
// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
for (i = 0; i < timeout_ms * 10 && (read32(&regs->config_load) &
I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) {
printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n",
@ -50,7 +50,7 @@ static void do_bus_clear(int bus)
udelay(100);
}
// 5. Set ENABLE to start the bus clear op
write32(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
for (i = 0; i < timeout_ms * 10 && (read32(&regs->bus_clear_config) &
I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) {
printk(BIOS_DEBUG, "%s: wait for bus clear completion\n",
@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read,
rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
while (header_words && tx_empty) {
write32(*headers++, &regs->tx_packet_fifo);
writel(*headers++, &regs->tx_packet_fifo);
header_words--;
tx_empty--;
}
@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read,
int todo = MIN(data_len, sizeof(word));
memcpy(&word, data, todo);
write32(word, &regs->tx_packet_fifo);
writel(word, &regs->tx_packet_fifo);
data_len -= todo;
data += sizeof(word);
tx_empty--;
@ -208,5 +208,5 @@ void i2c_init(unsigned bus)
{
struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base;
write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
writel(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
}

2
src/soc/nvidia/tegra/pingroup.c
View File

@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE;
void pingroup_set_config(int group_index, uint32_t config)
{
write32(config, &pingroup_regs[group_index]);
writel(config, &pingroup_regs[group_index]);
}
uint32_t pingroup_get_config(int group_index)

2
src/soc/nvidia/tegra/pinmux.c
View File

@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE;
void pinmux_set_config(int pin_index, uint32_t config)
{
write32(config, &pinmux_regs[pin_index]);
writel(config, &pinmux_regs[pin_index]);
}
uint32_t pinmux_get_config(int pin_index)

64
src/soc/nvidia/tegra/usb.c
View File

@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
{
int timeout = 1000;
write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
writel(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
/* TODO: Resets are long, find way to parallelize... or just use XHCI */
while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
/* wait for HC to reset */;
@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
}
/* Controller mode: HOST */
write32(3 << 0, &usb->usb_mode);
writel(3 << 0, &usb->usb_mode);
/* Parallel transceiver selct */
write32(type << 29, &usb->lpm_ctrl);
writel(type << 29, &usb->lpm_ctrl);
/* Tx FIFO Burst thresh */
write32(0x10 << 16, &usb->tx_fill_tuning);
writel(0x10 << 16, &usb->tx_fill_tuning);
}
/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
@ -157,61 +157,27 @@ void usb_setup_utmip(void *usb_base)
udelay(1);
/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
write32(0x8 << 25 | /* HS slew rate [10:4] */
0x3 << 22 | /* HS driver output 'SETUP' [6:4] */
0 << 21 | /* LS bias selection */
0 << 18 | /* PDZI pwrdn */
0 << 16 | /* PD2 pwrdn */
0 << 14 | /* PD pwrdn */
1 << 13 | /* (rst) HS receiver terminations */
0x1 << 10 | /* (rst) LS falling slew rate */
0x1 << 8 | /* (rst) LS rising slew rate */
0x4 << 0 | /* HS driver output 'SETUP' [3:0] */
0, &usb->utmip.xcvr0);
write32(0x7 << 18 | /* Termination range adjustment */
0 << 4 | /* PDDR pwrdn */
0 << 2 | /* PDCHRP pwrdn */
0 << 0 | /* PDDISC pwrdn */
0, &usb->utmip.xcvr1);
write32(1 << 19 | /* FS send initial J before sync(?) */
1 << 16 | /* (rst) Allow stuff error on SoP */
1 << 9 | /* (rst) Check disc only on EoP */
0, &usb->utmip.tx);
write32(0x2 << 30 | /* (rst) Keep pattern on active */
1 << 28 | /* (rst) Realign inertia on pkt */
0x1 << 24 | /* (rst) edges-1 to move sampling */
0x3 << 21 | /* (rst) squelch delay on EoP */
0x11 << 15 | /* cycles until IDLE */
0x10 << 10 | /* elastic input depth */
0, &usb->utmip.hsrx0);
writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0,
&usb->utmip.xcvr0);
writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1);
writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx);
writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0,
&usb->utmip.hsrx0);
/* U-Boot claims the USBD values for these are used across all UTMI+
* PHYs. That sounds so horribly wrong that I'm not going to implement
* it, but keep it in mind if we're ever not using the USBD port. */
write32(0x1 << 24 | /* HS disconnect detect level [2] */
1 << 23 | /* (rst) IDPD value */
1 << 22 | /* (rst) IDPD select */
1 << 11 | /* (rst) OTG pwrdn */
0 << 10 | /* bias pwrdn */
0x1 << 2 | /* HS disconnect detect level [1:0] */
0x2 << 0 | /* HS squelch detect level */
0, &usb->utmip.bias0);
writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0,
&usb->utmip.bias0);
write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */
1 << 2 | /* (rst) VBUS wakeup pwrdn */
0 << 0 | /* PDTRK pwrdn */
0, &usb->utmip.bias1);
writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1);
write32(0xffff << 16 | /* (rst) */
25 * khz / 10 << 0 | /* TODO: what's this, really? */
0, &usb->utmip.debounce);
writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce);
udelay(1);
setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
write32(1 << 12 | /* UTMI+ enable */
0 << 11 | /* UTMI+ reset */
0, &usb->suspend_ctrl);
writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl);
usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);

107
src/soc/nvidia/tegra124/clock.c
View File

@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
set_cntfrq(freq);
// Record the system timer frequency.
write32(freq, &sysctr->cntfid0);
writel(freq, &sysctr->cntfid0);
// Enable the system counter.
uint32_t cntcr = read32(&sysctr->cntcr);
cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
write32(cntcr, &sysctr->cntcr);
writel(cntcr, &sysctr->cntcr);
}
#define SOR0_CLK_SEL0 (1 << 14)
@ -243,25 +243,14 @@ static void init_utmip_pll(void)
clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
write32(80 << 16 | /* (rst) phy_divn */
1 << 8 | /* (rst) phy_divm */
0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
writel(80 << 16 | 1 << 8 | 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
0 << 16 | /* PLLU pwrdn */
0 << 14 | /* pll_enable pwrdn */
0 << 12 | /* pll_active pwrdn */
CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
0, &clk_rst->utmip_pll_cfg1);
writel(CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0,
&clk_rst->utmip_pll_cfg1);
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
0 << 4 | /* SAMP_C/USB3 pwrdn */
0 << 2 | /* SAMP_B/XHOST pwrdn */
0 << 0 | /* SAMP_A/USBD pwrdn */
0, &clk_rst->utmip_pll_cfg2);
writel(0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
&clk_rst->utmip_pll_cfg2);
setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
}
@ -398,8 +387,8 @@ clock_display(u32 frequency)
* been determined through trial and error (must lead to div 13 at 24MHz). */
void clock_early_uart(void)
{
write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE |
CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta);
writel(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
&clk_rst->clk_src_uarta);
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
udelay(2);
clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
@ -486,28 +475,24 @@ void clock_cpu0_config(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
write32((uintptr_t)_estack, &maincpu_stack_pointer);
write32((uintptr_t)entry, &maincpu_entry_point);
write32((uintptr_t)&maincpu_setup, evp_cpu_reset);
writel((uintptr_t)_estack, &maincpu_stack_pointer);
writel((uintptr_t)entry, &maincpu_entry_point);
writel((uintptr_t)&maincpu_setup, evp_cpu_reset);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
// Set up cclk_brst and divider.
write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
(CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
(CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
(CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) |
(CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
&clk_rst->cclk_brst_pol);
write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
&clk_rst->super_cclk_div);
writel((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
&clk_rst->cclk_brst_pol);
writel(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
&clk_rst->super_cclk_div);
// Enable the clocks for CPUs 0-3.
uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
writel(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
// Enable other CPU related clocks.
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
@ -518,36 +503,23 @@ void clock_cpu0_config(void *entry)
void clock_cpu0_remove_reset(void)
{
// Disable the reset on the non-CPU parts of the fast cluster.
write32(CRC_RST_CPUG_CLR_NONCPU,
&clk_rst->rst_cpug_cmplx_clr);
writel(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr);
// Disable the various resets on the CPUs.
write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 |
CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 |
CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 |
CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 |
CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
&clk_rst->rst_cpug_cmplx_clr);
writel(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
&clk_rst->rst_cpug_cmplx_clr);
// Disable the reset on the non-CPU parts of the slow cluster.
write32(CRC_RST_CPULP_CLR_NONCPU,
&clk_rst->rst_cpulp_cmplx_clr);
writel(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr);
// Disable the various resets on the LP CPU.
write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
&clk_rst->rst_cpulp_cmplx_clr);
writel(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
&clk_rst->rst_cpulp_cmplx_clr);
}
void clock_halt_avp(void)
{
for (;;) {
write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
&flow->halt_cop_events);
writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
&flow->halt_cop_events);
}
}
@ -564,15 +536,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
write32(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT |
TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate);
write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) <<
PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN |
PLL_OUT_RSTN, &clk_rst->pllc_out);
write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
&clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
writel(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
&clk_rst->clk_sys_rate);
writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
&clk_rst->pllc_out);
writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
&clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
@ -590,16 +559,10 @@ void clock_init(void)
clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
&clk_rst->pllp_outa);
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
&clk_rst->pllp_outb);
writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
&clk_rst->pllp_outa);
writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
&clk_rst->pllp_outb);
/* init pllx */
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,

87
src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
View File

@ -282,17 +282,17 @@ inline static void write32(uint32_t val, void *addr)
inline static void setbits32(uint32_t bits, void *addr)
{
write32(read32(addr) | bits, addr);
writel(read32(addr) | bits, addr);
}
inline static void clrbits32(uint32_t bits, void *addr)
{
write32(read32(addr) & ~bits, addr);
writel(read32(addr) & ~bits, addr);
}
static void __attribute__((noreturn)) reset(void)
{
write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
halt();
}
@ -337,7 +337,7 @@ static void config_oscillator(void)
osc_ctrl &= ~OSC_XOFS_MASK;
osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
osc_ctrl |= OSC_XOE;
write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
}
static void config_pllu(void)
@ -382,17 +382,17 @@ static void config_pllu(void)
// Configure PLLU.
uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
write32(base, clk_rst_pllu_base_ptr);
writel(base, clk_rst_pllu_base_ptr);
uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
(lfcon << PLLU_LFCON_SHIFT);
write32(misc, clk_rst_pllu_misc_ptr);
writel(misc, clk_rst_pllu_misc_ptr);
// Enable PLLU.
base &= ~PLLU_BYPASS;
base |= PLLU_ENABLE;
write32(base, clk_rst_pllu_base_ptr);
writel(base, clk_rst_pllu_base_ptr);
misc |= PLLU_LOCK_ENABLE;
write32(misc, clk_rst_pllu_misc_ptr);
writel(misc, clk_rst_pllu_misc_ptr);
}
static void config_tsc(void)
@ -400,26 +400,26 @@ static void config_tsc(void)
// Tell the TSC the oscillator frequency.
switch (get_osc_freq()) {
case OSC_FREQ_12:
write32(12000000, sysctr_cntfid0_ptr);
writel(12000000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_48:
write32(48000000, sysctr_cntfid0_ptr);
writel(48000000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_16P8:
write32(16800000, sysctr_cntfid0_ptr);
writel(16800000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_19P2:
write32(19200000, sysctr_cntfid0_ptr);
writel(19200000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_38P4:
write32(38400000, sysctr_cntfid0_ptr);
writel(38400000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_26:
write32(26000000, sysctr_cntfid0_ptr);
writel(26000000, sysctr_cntfid0_ptr);
break;
default:
// Default to 13MHz.
write32(13000000, sysctr_cntfid0_ptr);
writel(13000000, sysctr_cntfid0_ptr);
break;
}
@ -430,8 +430,8 @@ static void config_tsc(void)
static void enable_cpu_clocks(void)
{
// Enable the CPU complex clock.
write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
}
@ -441,7 +441,7 @@ static void enable_cpu_clocks(void)
static void config_core_sight(void)
{
// Enable the CoreSight clock.
write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
/*
* De-assert CoreSight reset.
@ -449,22 +449,22 @@ static void config_core_sight(void)
* now. It will be restored to its original clock source
* when the CPU-side restoration code runs.
*/
write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
}
static void config_mselect(void)
{
// Set MSELECT clock source to PLLP with 1:4 divider.
write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
clk_rst_clk_src_mselect_ptr);
writel((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
clk_rst_clk_src_mselect_ptr);
// Enable clock to MSELECT.
write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
writel(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
udelay(2);
// Bring MSELECT out of reset.
write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
writel(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
}
@ -474,19 +474,16 @@ static void config_mselect(void)
static void clear_cpu_resets(void)
{
// Take the non-cpu of the G and LP clusters out of reset.
write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
writel(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
writel(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
// Clear software controlled reset of the slow cluster.
write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
clk_rst_rst_cpulp_cmplx_clr_ptr);
writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
clk_rst_rst_cpulp_cmplx_clr_ptr);
// Clear software controlled reset of the fast cluster.
write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
clk_rst_rst_cpug_cmplx_clr_ptr);
writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
clk_rst_rst_cpug_cmplx_clr_ptr);
}
@ -516,7 +513,7 @@ static void power_on_partition(unsigned id)
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
// Partition is not on. Turn it on.
write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
// Wait until the partition is powerd on.
while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@ -546,8 +543,8 @@ static void power_on_main_cpu(void)
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
write32(orig_timer * (204000000 / 32768),
pmc_ctlr_cpupwrgood_timer_ptr);
writel(orig_timer * (204000000 / 32768),
pmc_ctlr_cpupwrgood_timer_ptr);
if (wakeup_on_lp()) {
power_on_partition(PARTID_C1NC);
@ -559,7 +556,7 @@ static void power_on_main_cpu(void)
}
// Restore the original PMC_CPUPWRGOOD_TIMER.
write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
}
@ -581,17 +578,17 @@ void lp0_resume(void)
flow_ctlr_cluster_control_ptr);
// Program SUPER_CCLK_DIVIDER.
write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
config_core_sight();
config_pllu();
// Set the CPU reset vector.
write32(get_wakeup_vector(), evp_cpu_reset_ptr);
writel(get_wakeup_vector(), evp_cpu_reset_ptr);
// Select CPU complex clock source.
write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
config_mselect();
@ -602,14 +599,14 @@ void lp0_resume(void)
uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
config_tsc();
// Disable VPR.
write32(0, mc_video_protect_size_mb_ptr);
write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
writel(0, mc_video_protect_size_mb_ptr);
writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
enable_cpu_clocks();
@ -622,8 +619,8 @@ void lp0_resume(void)
// Halt the AVP.
while (1)
write32(FLOW_MODE_STOP | EVENT_JTAG,
flow_ctlr_halt_cop_events_ptr);
writel(FLOW_MODE_STOP | EVENT_JTAG,
flow_ctlr_halt_cop_events_ptr);
}

6
src/soc/nvidia/tegra124/power.c
View File

@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id)
pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
write32(pwrgate_toggle, &pmc->pwrgate_toggle);
writel(pwrgate_toggle, &pmc->pwrgate_toggle);
// Wait for the request to be accepted.
while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void)
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz),
* set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s).
*/
write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
uint32_t cntrl = read32(&pmc->cntrl);
cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
write32(cntrl, &pmc->cntrl);
writel(cntrl, &pmc->cntrl);
power_ungate_partition(POWER_PARTID_CRAIL);

22
src/soc/nvidia/tegra124/spi.c
View File

@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
else
val |= SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
writel(val, &regs->command1);
return 0;
}
@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
else
val &= ~SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
writel(val, &regs->command1);
}
static void dump_fifo_status(struct tegra_spi_channel *spi)
@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
* PIO transfers */
write32(todo - 1, &spi->regs->dma_blk);
writel(todo - 1, &spi->regs->dma_blk);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
while (to_fifo) {
write32(*p, &spi->regs->tx_fifo);
writel(*p, &spi->regs->tx_fifo);
p++;
to_fifo--;
}
@ -493,11 +493,11 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* ensure bytes to send will be visible to DMA controller */
dcache_clean_by_mva(spi->out_buf, bytes);
write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
writel((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
writel((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
write32(wcount, &spi->dma_out->regs->wcount);
writel(wcount, &spi->dma_out->regs->wcount);
} else {
spi->dma_in = dma_claim();
if (!spi->dma_in)
@ -506,15 +506,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* avoid data collisions */
dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
writel((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
writel((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
write32(wcount, &spi->dma_in->regs->wcount);
writel(wcount, &spi->dma_in->regs->wcount);
}
/* BLOCK_SIZE starts at n-1 */
write32(todo - 1, &spi->regs->dma_blk);
writel(todo - 1, &spi->regs->dma_blk);
return todo;
}

19
src/soc/nvidia/tegra124/uart.c
View File

@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
tegra124_uart_tx_flush(uart_ptr);
// Disable interrupts.
write8(0, &uart_ptr->ier);
writeb(0, &uart_ptr->ier);
// Force DTR and RTS to high.
write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
// Set line configuration, access divisor latches.
write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
// Set the divisor.
write8(divisor & 0xff, &uart_ptr->dll);
write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
writeb(divisor & 0xff, &uart_ptr->dll);
writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
// Hide the divisor latches.
write8(line_config, &uart_ptr->lcr);
writeb(line_config, &uart_ptr->lcr);
// Enable FIFOs, and clear receive and transmit.
write8(UART8250_FCR_FIFO_EN |
UART8250_FCR_CLEAR_RCVR |
UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
&uart_ptr->fcr);
}
static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
write8(data, &uart_ptr->thr);
writeb(data, &uart_ptr->thr);
}
static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr)

6
src/soc/nvidia/tegra132/addressmap.c
View File

@ -187,9 +187,9 @@ void trustzone_region_init(void)
return;
/* Set the carveout region. */
write32(tz_base_mib << 20, &mc->security_cfg0);
write32(tz_size_mib, &mc->security_cfg1);
writel(tz_base_mib << 20, &mc->security_cfg0);
writel(tz_size_mib, &mc->security_cfg1);
/* Enable SMMU translations */
write32(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
writel(MC_SMMU_CONFIG_ENABLE, &mc->smmu_config);
}

2
src/soc/nvidia/tegra132/bootblock.c
View File

@ -46,7 +46,7 @@ static void save_odmdata(void)
bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT));
if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) {
odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT));
write32(odmdata, &pmc->odmdata);
writel(odmdata, &pmc->odmdata);
}
}

14
src/soc/nvidia/tegra132/ccplex.c
View File

@ -46,12 +46,12 @@ static int ccplex_start(void)
struct tegra_pmc_regs * const pmc = PMC_REGS;
/* Set the handshake bit to be knocked down. */
write32(handshake_mask, &pmc->scratch118);
writel(handshake_mask, &pmc->scratch118);
/* Assert nCXRSET[1] */
reg = read32(CLK_RST_REG(rst_cpu_cmplx_set));
reg |= cxreset1_mask;
write32(reg, CLK_RST_REG(rst_cpu_cmplx_set));
writel(reg, CLK_RST_REG(rst_cpu_cmplx_set));
stopwatch_init_msecs_expire(&sw, timeout_ms);
while (1) {
@ -140,14 +140,14 @@ static void request_ram_repair(void)
/* Perform cluster 0 ram repair */
reg = read32(&flow->ram_repair);
reg |= req;
write32(reg, &flow->ram_repair);
writel(reg, &flow->ram_repair);
while ((read32(&flow->ram_repair) & sts) != sts)
;
/* Perform cluster 1 ram repair */
reg = read32(&flow->ram_repair_cluster1);
reg |= req;
write32(reg, &flow->ram_repair_cluster1);
writel(reg, &flow->ram_repair_cluster1);
while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
;
@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void)
static void start_common_clocks(void)
{
/* Clear fast CPU partition reset. */
write32(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
/* Clear reset of L2 and CoreSight components. */
write32(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
CLK_RST_REG(rst_cpug_cmplx_clr));
writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
CLK_RST_REG(rst_cpug_cmplx_clr));
}
void ccplex_cpu_start(void *entry_addr)

66
src/soc/nvidia/tegra132/clock.c
View File

@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
set_cntfrq(freq);
/* Record the system timer frequency. */
write32(freq, &sysctr->cntfid0);
writel(freq, &sysctr->cntfid0);
/* Enable the system counter. */
uint32_t cntcr = read32(&sysctr->cntcr);
cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
write32(cntcr, &sysctr->cntcr);
writel(cntcr, &sysctr->cntcr);
}
#define SOR0_CLK_SEL0 (1 << 14)
@ -243,25 +243,14 @@ static void init_utmip_pll(void)
clrbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
write32(80 << 16 | /* (rst) phy_divn */
1 << 8 | /* (rst) phy_divm */
0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
writel(80 << 16 | 1 << 8 | 0, CLK_RST_REG(utmip_pll_cfg0));/* 960MHz * 1 / 80 == 12 MHz */
write32(div_round_up(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
0 << 16 | /* PLLU pwrdn */
0 << 14 | /* pll_enable pwrdn */
0 << 12 | /* pll_active pwrdn */
div_round_up(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
0, CLK_RST_REG(utmip_pll_cfg1));
writel(div_round_up(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | div_round_up(khz, 102) << 0 | 0,
CLK_RST_REG(utmip_pll_cfg1));
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
div_round_up(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
div_round_up(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
0 << 4 | /* SAMP_C/USB3 pwrdn */
0 << 2 | /* SAMP_B/XHOST pwrdn */
0 << 0 | /* SAMP_A/USBD pwrdn */
0, CLK_RST_REG(utmip_pll_cfg2));
writel(0 << 24 | div_round_up(khz, 3200) << 18 | div_round_up(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
CLK_RST_REG(utmip_pll_cfg2));
setbits_le32(CLK_RST_REG(utmip_pll_cfg2), 1 << 30); /* PHY_XTAL_CLKEN */
}
@ -398,9 +387,8 @@ u32 clock_configure_plld(u32 frequency)
* been determined through trial and error (must lead to div 13 at 24MHz). */
void clock_early_uart(void)
{
write32(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT |
CLK_UART_DIV_OVERRIDE |
CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), CLK_RST_REG(clk_src_uarta));
writel(CLK_SRC_DEV_ID(UARTA, CLK_M) << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
CLK_RST_REG(clk_src_uarta));
clock_enable_clear_reset_l(CLK_L_UARTA);
}
@ -503,8 +491,8 @@ void clock_cpu0_config(void)
*/
do {
if (readl(&clst_clk->misc_ctrl) & CLK_SWITCH_MATCH) {
write32((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
&clst_clk->cclk_brst_pol);
writel((CC_CCLK_BRST_POL_PLLX_OUT0_LJ << 28),
&clst_clk->cclk_brst_pol);
break;
}
@ -524,9 +512,8 @@ void clock_cpu0_config(void)
void clock_halt_avp(void)
{
for (;;)
write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
&flow->halt_cop_events);
writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
&flow->halt_cop_events);
}
void clock_init(void)
@ -542,13 +529,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */
write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_CLKEN | PLL_OUT_RSTN, CLK_RST_REG(pllc_out));
write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */
writel(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
CLK_RST_REG(clk_sys_rate)); /* pclk = hclk = sclk/2 */
writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
CLK_RST_REG(pllc_out));
writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
CLK_RST_REG(sclk_brst_pol)); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
@ -563,16 +549,10 @@ void clock_init(void)
OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
CLK_RST_REG(pllp_outa));
write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
(CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
CLK_RST_REG(pllp_outb));
writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
CLK_RST_REG(pllp_outa));
writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
CLK_RST_REG(pllp_outb));
/* init pllu */
init_pll(CLK_RST_REG(pllu_base), CLK_RST_REG(pllu_misc),

10
src/soc/nvidia/tegra132/cpu.c
View File

@ -40,15 +40,15 @@ static void enable_core_clocks(int cpu)
/* Clear reset of CPU components. */
if (cpu == 0)
write32(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
writel(cpu0_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
else
write32(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
writel(cpu1_clocks, CLK_RST_REG(rst_cpug_cmplx_clr));
}
static void set_armv8_32bit_reset_vector(uintptr_t entry)
{
void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
write32(entry, evp_cpu_reset_vector);
writel(entry, evp_cpu_reset_vector);
}
static void set_armv8_64bit_reset_vector(uintptr_t entry)
@ -56,8 +56,8 @@ static void set_armv8_64bit_reset_vector(uintptr_t entry)
struct tegra_pmc_regs * const pmc = PMC_REGS;
/* Currently assume 32-bit addresses only. */
write32(entry, &pmc->secure_scratch34);
write32(0, &pmc->secure_scratch35);
writel(entry, &pmc->secure_scratch34);
writel(0, &pmc->secure_scratch35);
}
void cpu_prepare_startup(void *entry_64)

2
src/soc/nvidia/tegra132/dsi.c
View File

@ -869,7 +869,7 @@ static int dsi_enable(struct soc_nvidia_tegra132_config *config)
tegra_output_dsi_setup_clock(dsi_a, config);
/* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */
write32(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
writel(DSIB_MODE_DSI, (unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0);
/* configure phy interface timing registers */
tegra_dsi_set_phy_timing(dsi_a);

2
src/soc/nvidia/tegra132/flow_ctrl.c
View File

@ -62,7 +62,7 @@ static uint32_t flowctrl_read_cpu_csr(int cpu)
static void flowctrl_write_cpu_csr(int cpu, uint32_t val)
{
write32(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
writel(val, tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
val = readl(tegra_flowctrl_base + flowctrl_offset_cpu_csr[cpu]);
}

4
src/soc/nvidia/tegra132/i2c6.c
View File

@ -43,7 +43,7 @@ static void remove_clamps(int id)
return;
/* Remove clamp */
write32((1 << id), &pmc->remove_clamping_cmd);
writel((1 << id), &pmc->remove_clamping_cmd);
/* Wait for clamp off */
while (partition_clamp_on(id))
@ -86,7 +86,7 @@ void soc_configure_i2c6pad(void)
soc_configure_host1x();
/* Now we can write the I2C6 mux in DPAUX */
write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
writel(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
/*
* Delay before turning off Host1X/DPAUX clocks.

78
src/soc/nvidia/tegra132/lp0/tegra_lp0_resume.c
View File

@ -261,17 +261,17 @@ inline static void write32(uint32_t val, void *addr)
inline static void setbits32(uint32_t bits, void *addr)
{
write32(read32(addr) | bits, addr);
writel(read32(addr) | bits, addr);
}
inline static void clrbits32(uint32_t bits, void *addr)
{
write32(read32(addr) & ~bits, addr);
writel(read32(addr) & ~bits, addr);
}
static void __attribute__((noreturn)) reset(void)
{
write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
halt();
}
@ -370,18 +370,18 @@ static void enable_uart(void)
clrbits32(uart_mask, uart_rst_reg);
/* Program UART clock source: PLLP (408000000) */
write32(0, uart_clk_source);
writel(0, uart_clk_source);
/* Program 115200n8 to the uart port */
/* baud-rate of 115200 */
write32(LCR_DLAB, (uart_base + UART_LCR));
write32((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
write32((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
writel(LCR_DLAB, (uart_base + UART_LCR));
writel((UART_RATE_115200 & 0xff), (uart_base + UART_THR_DLAB));
writel((UART_RATE_115200 >> 8), (uart_base + UART_IER_DLAB));
/* 8-bit and no parity */
write32(LCR_WD_SIZE_8, (uart_base + UART_LCR));
writel(LCR_WD_SIZE_8, (uart_base + UART_LCR));
/* enable and clear RX/TX FIFO */
write32((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
(uart_base + UART_IIR_FCR));
writel((FCR_TX_CLR + FCR_RX_CLR + FCR_EN_FIFO),
(uart_base + UART_IIR_FCR));
}
/* Accessors. */
@ -401,7 +401,7 @@ static unsigned get_osc_freq(void)
static void enable_jtag(void)
{
write32(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
writel(PP_CONFIG_CTL_JTAG, misc_pp_config_ctl_ptr);
}
/* Clock configuration. */
@ -417,7 +417,7 @@ static void config_oscillator(void)
osc_ctrl &= ~OSC_XOFS_MASK;
osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
osc_ctrl |= OSC_XOE;
write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
}
static void config_pllu(void)
@ -462,24 +462,24 @@ static void config_pllu(void)
// Configure PLLU.
uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
write32(base, clk_rst_pllu_base_ptr);
writel(base, clk_rst_pllu_base_ptr);
uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
(lfcon << PLLU_LFCON_SHIFT);
write32(misc, clk_rst_pllu_misc_ptr);
writel(misc, clk_rst_pllu_misc_ptr);
// Enable PLLU.
base &= ~PLLU_BYPASS;
base |= PLLU_ENABLE;
write32(base, clk_rst_pllu_base_ptr);
writel(base, clk_rst_pllu_base_ptr);
misc |= PLLU_LOCK_ENABLE;
write32(misc, clk_rst_pllu_misc_ptr);
writel(misc, clk_rst_pllu_misc_ptr);
}
static void enable_cpu_clocks(void)
{
// Enable the CPU complex clock.
write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
}
@ -489,7 +489,7 @@ static void enable_cpu_clocks(void)
static void config_core_sight(void)
{
// Enable the CoreSight clock.
write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
/*
* De-assert CoreSight reset.
@ -497,7 +497,7 @@ static void config_core_sight(void)
* now. It will be restored to its original clock source
* when the CPU-side restoration code runs.
*/
write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
}
@ -508,11 +508,11 @@ static void clear_cpu_resets(void)
/* Hold CPU1 in reset */
setbits32(SET_CXRESET1, clk_rst_rst_cpulp_cmplx_set_ptr);
write32(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
clk_rst_rst_cpug_cmplx_clr_ptr);
writel(CLR_NONCPURESET | CLR_L2RESET | CLR_PRESETDBG,
clk_rst_rst_cpug_cmplx_clr_ptr);
write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
clk_rst_rst_cpug_cmplx_clr_ptr);
writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
clk_rst_rst_cpug_cmplx_clr_ptr);
}
@ -542,7 +542,7 @@ static void power_on_partition(unsigned id)
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
// Partition is not on. Turn it on.
write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
// Wait until the partition is powerd on.
while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@ -572,15 +572,15 @@ static void power_on_main_cpu(void)
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
write32(orig_timer * (204000000 / 32768),
pmc_ctlr_cpupwrgood_timer_ptr);
writel(orig_timer * (204000000 / 32768),
pmc_ctlr_cpupwrgood_timer_ptr);
power_on_partition(PARTID_CRAIL);
power_on_partition(PARTID_C0NC);
power_on_partition(PARTID_CE0);
// Restore the original PMC_CPUPWRGOOD_TIMER.
write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
}
@ -609,7 +609,7 @@ void lp0_resume(void)
config_oscillator();
// Program SUPER_CCLK_DIVIDER.
write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
config_core_sight();
@ -623,12 +623,12 @@ void lp0_resume(void)
* T132 always resets to AARCH32 and SW needs to write RMR_EL3
* to bootstrap into AARCH64.
*/
write32(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
write32(0, pmc_ctlr_secure_scratch35_ptr);
write32((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
writel(get_wakeup_vector(), pmc_ctlr_secure_scratch34_ptr);
writel(0, pmc_ctlr_secure_scratch35_ptr);
writel((uint32_t)aarch64_trampoline, evp_cpu_reset_ptr);
// Select CPU complex clock source.
write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
// Disable PLLX since it isn't used as CPU clock source.
clrbits32(PLLX_ENABLE, clk_rst_pllx_base_ptr);
@ -637,12 +637,12 @@ void lp0_resume(void)
uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
// Disable VPR.
write32(0, mc_video_protect_size_mb_ptr);
write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
writel(0, mc_video_protect_size_mb_ptr);
writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
mc_video_protect_reg_ctrl_ptr);
enable_cpu_clocks();
@ -655,8 +655,8 @@ void lp0_resume(void)
// Halt the AVP.
while (1)
write32(FLOW_MODE_STOP | EVENT_JTAG,
flow_ctlr_halt_cop_events_ptr);
writel(FLOW_MODE_STOP | EVENT_JTAG,
flow_ctlr_halt_cop_events_ptr);
}

14
src/soc/nvidia/tegra132/padconfig.c
View File

@ -36,7 +36,7 @@ static inline uint32_t pad_get_pinmux(int index)
static inline void pad_set_pinmux(int index, uint32_t reg)
{
return write32(reg, &pinmux_regs[index]);
return writel(reg, &pinmux_regs[index]);
}
static inline void pad_set_gpio_out(int gpio_index, int val)
@ -45,10 +45,10 @@ static inline void pad_set_gpio_out(int gpio_index, int val)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
&regs->out_value_mask[port]);
write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
&regs->out_enable_mask[port]);
writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (val << bit),
&regs->out_value_mask[port]);
writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (1 << bit),
&regs->out_enable_mask[port]);
}
static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
@ -57,8 +57,8 @@ static inline void pad_set_mode(int gpio_index, int sfio_or_gpio)
int port = gpio_index_to_port(gpio_index);
int bit = gpio_to_bit(gpio_index);
write32((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
&regs->config_mask[port]);
writel((1 << (bit + GPIO_GPIOS_PER_PORT)) | (sfio_or_gpio << bit),
&regs->config_mask[port]);
}
static inline void pad_set_gpio_mode(int gpio_index)

2
src/soc/nvidia/tegra132/power.c
View File

@ -41,7 +41,7 @@ void power_ungate_partition(uint32_t id)
pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
write32(pwrgate_toggle, &pmc->pwrgate_toggle);
writel(pwrgate_toggle, &pmc->pwrgate_toggle);
/* Wait for the request to be accepted. */
while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)

6
src/soc/nvidia/tegra132/soc.c
View File

@ -83,9 +83,9 @@ static void lock_down_vpr(void)
{
struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
write32(0, &regs->video_protect_bom);
write32(0, &regs->video_protect_size_mb);
write32(1, &regs->video_protect_reg_ctrl);
writel(0, &regs->video_protect_bom);
writel(0, &regs->video_protect_size_mb);
writel(1, &regs->video_protect_reg_ctrl);
}
static void soc_init(device_t dev)

24
src/soc/nvidia/tegra132/spi.c
View File

@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
else
val |= SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
writel(val, &regs->command1);
return 0;
}
@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
else
val &= ~SPI_CMD1_CS_SW_VAL;
write32(val, &regs->command1);
writel(val, &regs->command1);
}
static void dump_fifo_status(struct tegra_spi_channel *spi)
@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
* PIO transfers */
write32(todo - 1, &spi->regs->dma_blk);
writel(todo - 1, &spi->regs->dma_blk);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
while (to_fifo) {
write32(*p, &spi->regs->tx_fifo);
writel(*p, &spi->regs->tx_fifo);
p++;
to_fifo--;
}
@ -493,11 +493,12 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* ensure bytes to send will be visible to DMA controller */
dcache_clean_by_mva(spi->out_buf, bytes);
write32((uintptr_t)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
write32((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
writel((uintptr_t) & spi->regs->tx_fifo,
&spi->dma_out->regs->apb_ptr);
writel((uintptr_t)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
write32(wcount, &spi->dma_out->regs->wcount);
writel(wcount, &spi->dma_out->regs->wcount);
} else {
spi->dma_in = dma_claim();
if (!spi->dma_in)
@ -506,15 +507,16 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* avoid data collisions */
dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
write32((uintptr_t)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
write32((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
writel((uintptr_t)&spi->regs->rx_fifo,
&spi->dma_in->regs->apb_ptr);
writel((uintptr_t)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
write32(wcount, &spi->dma_in->regs->wcount);
writel(wcount, &spi->dma_in->regs->wcount);
}
/* BLOCK_SIZE starts at n-1 */
write32(todo - 1, &spi->regs->dma_blk);
writel(todo - 1, &spi->regs->dma_blk);
return todo;
}

19
src/soc/nvidia/tegra132/uart.c
View File

@ -63,20 +63,19 @@ static void tegra132_uart_init(struct tegra132_uart *uart_ptr)
tegra132_uart_tx_flush(uart_ptr);
// Disable interrupts.
write8(0, &uart_ptr->ier);
writeb(0, &uart_ptr->ier);
// Force DTR and RTS to high.
write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
// Set line configuration, access divisor latches.
write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
// Set the divisor.
write8(divisor & 0xff, &uart_ptr->dll);
write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
writeb(divisor & 0xff, &uart_ptr->dll);
writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
// Hide the divisor latches.
write8(line_config, &uart_ptr->lcr);
writeb(line_config, &uart_ptr->lcr);
// Enable FIFOs, and clear receive and transmit.
write8(UART8250_FCR_FIFO_EN |
UART8250_FCR_CLEAR_RCVR |
UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
&uart_ptr->fcr);
}
static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
@ -89,7 +88,7 @@ static unsigned char tegra132_uart_rx_byte(struct tegra132_uart *uart_ptr)
static void tegra132_uart_tx_byte(struct tegra132_uart *uart_ptr, unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
write8(data, &uart_ptr->thr);
writeb(data, &uart_ptr->thr);
}
static void tegra132_uart_tx_flush(struct tegra132_uart *uart_ptr)

27
src/soc/qualcomm/ipq806x/clock.c
View File

@ -126,22 +126,17 @@ void nand_clock_config(void)
void usb_clock_config(void)
{
/* Magic clock initialization numbers, nobody knows how they work... */
write32(0x10, USB30_MASTER_CLK_CTL_REG);
write32(0x10, USB30_1_MASTER_CLK_CTL_REG);
write32(0x500DF, USB30_MASTER_CLK_MD);
write32(0xE40942, USB30_MASTER_CLK_NS);
write32(0x100D7, USB30_MOC_UTMI_CLK_MD);
write32(0xD80942, USB30_MOC_UTMI_CLK_NS);
write32(0x10, USB30_MOC_UTMI_CLK_CTL);
write32(0x10, USB30_1_MOC_UTMI_CLK_CTL);
writel(0x10, USB30_MASTER_CLK_CTL_REG);
writel(0x10, USB30_1_MASTER_CLK_CTL_REG);
writel(0x500DF, USB30_MASTER_CLK_MD);
writel(0xE40942, USB30_MASTER_CLK_NS);
writel(0x100D7, USB30_MOC_UTMI_CLK_MD);
writel(0xD80942, USB30_MOC_UTMI_CLK_NS);
writel(0x10, USB30_MOC_UTMI_CLK_CTL);
writel(0x10, USB30_1_MOC_UTMI_CLK_CTL);
write32(1 << 5 | /* assert port2 HS PHY async reset */
1 << 4 | /* assert master async reset */
1 << 3 | /* assert sleep async reset */
1 << 2 | /* assert MOC UTMI async reset */
1 << 1 | /* assert power-on async reset */
1 << 0 | /* assert PHY async reset */
0, USB30_RESET);
writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0,
USB30_RESET);
udelay(5);
write32(0, USB30_RESET); /* deassert all USB resets again */
writel(0, USB30_RESET); /* deassert all USB resets again */
}

67
src/soc/qualcomm/ipq806x/usb.c
View File

@ -101,33 +101,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE;
static void setup_dwc3(struct usb_dwc3 *dwc3)
{
write32(0x1 << 31 | /* assert PHY soft reset */
0x1 << 25 | /* (default) U1/U2 exit fail -> recovery? */
0x1 << 24 | /* (default) activate PHY low power states */
0x1 << 19 | /* (default) PHY low power delay value */
0x1 << 18 | /* (default) activate PHY low power delay */
0x1 << 1 | /* (default) Tx deemphasis value */
0x1 << 0 | /* (default) elastic buffer mode */
0, &dwc3->usb3pipectl);
writel(0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0,
&dwc3->usb3pipectl);
write32(0x1 << 31 | /* assert PHY soft reset */
0x9 << 10 | /* (default) PHY clock turnaround 8-bit UTMI+ */
0x1 << 8 | /* (default) enable PHY sleep in L1 */
0x1 << 6 | /* (default) enable PHY suspend */
0, &dwc3->usb2phycfg);
writel(0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0,
&dwc3->usb2phycfg);
write32(0x2 << 19 | /* (default) suspend clock scaling */
0x1 << 16 | /* retry SS three times before HS downgrade */
0x1 << 12 | /* port capability HOST */
0x1 << 11 | /* assert core soft reset */
0x1 << 10 | /* (default) sync ITP to refclk */
0x1 << 2 | /* U2 exit after 8us LFPS (instead of 248ns) */
0, &dwc3->ctl);
writel(0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0,
&dwc3->ctl);
write32(0x32 << 22 | /* (default) reference clock period in ns */
0x1 << 15 | /* (default) XHCI compliant device addressing */
0x10 << 0 | /* (default) devices time out after 32us */
0, &dwc3->uctl);
writel(0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0, &dwc3->uctl);
udelay(5);
@ -138,34 +121,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
static void setup_phy(struct usb_qc_phy *phy)
{
write32(0x1 << 24 | /* Indicate VBUS power present */
0x1 << 8 | /* Enable USB3 ref clock to prescaler */
0x1 << 7 | /* assert SS PHY reset */
0x19 << 0 | /* (default) reference clock multiplier */
0, &phy->ss_phy_ctrl);
writel(0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0,
&phy->ss_phy_ctrl);
write32(0x1 << 26 | /* (default) unclamp DPSE/DMSE VLS */
0x1 << 25 | /* (default) select freeclk for utmi_clk */
0x1 << 24 | /* (default) unclamp DMSE VLS */
0x1 << 21 | /* (default) enable UTMI clock */
0x1 << 20 | /* set OTG VBUS as valid */
0x1 << 18 | /* use ref clock from core */
0x1 << 17 | /* (default) unclamp DPSE VLS */
0x1 << 11 | /* force xo/bias/pll to stay on in suspend */
0x1 << 9 | /* (default) unclamp IDHV */
0x1 << 8 | /* (default) unclamp VLS (again???) */
0x1 << 7 | /* (default) unclamp HV VLS */
0x7 << 4 | /* select frequency (no idea which one) */
0x1 << 1 | /* (default) "retention enable" */
0, &phy->hs_phy_ctrl);
writel(0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0,
&phy->hs_phy_ctrl);
write32(0x6e << 20 | /* full TX swing amplitude */
0x20 << 14 | /* (default) 6dB TX deemphasis */
0x17 << 8 | /* 3.5dB TX deemphasis */
0x9 << 3 | /* (default) LoS detector level */
0, &phy->ss_phy_param1);
writel(0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0,
&phy->ss_phy_param1);
write32(0x1 << 2, &phy->general_cfg); /* set XHCI 1.00 compliance */
writel(0x1 << 2, &phy->general_cfg); /* set XHCI 1.00 compliance */
udelay(5);
clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
@ -176,9 +141,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data)
int usec = 100;
if (capture_reg)
write32(data, capture_reg);
writel(data, capture_reg);
write32(0x1 << 0, acknowledge_bit);
writel(0x1 << 0, acknowledge_bit);
while (read32(acknowledge_bit) && --usec)
udelay(1);

20
src/soc/rockchip/rk3288/crypto.c
View File

@ -80,17 +80,17 @@ int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg,
return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED;
}
write32(RK_SETBITS(1 << 6), &crypto->ctrl); /* Assert HASH_FLUSH */
writel(RK_SETBITS(1 << 6), &crypto->ctrl); /* Assert HASH_FLUSH */
udelay(1); /* for 10+ cycles to */
write32(RK_CLRBITS(1 << 6), &crypto->ctrl); /* clear out old hash */
writel(RK_CLRBITS(1 << 6), &crypto->ctrl); /* clear out old hash */
/* Enable DMA byte swapping for little-endian bus (Byteswap_??FIFO) */
write32(1 << 5 | 1 << 4 | 1 << 3, &crypto->conf);
writel(1 << 5 | 1 << 4 | 1 << 3, &crypto->conf);
write32(HRDMA_ERR | HRDMA_DONE, &crypto->intena); /* enable interrupt */
writel(HRDMA_ERR | HRDMA_DONE, &crypto->intena); /* enable interrupt */
write32(data_size, &crypto->hash_msg_len); /* program total size */
write32(1 << 3 | 0x2, &crypto->hash_ctrl); /* swap DOUT, SHA256 */
writel(data_size, &crypto->hash_msg_len); /* program total size */
writel(1 << 3 | 0x2, &crypto->hash_ctrl); /* swap DOUT, SHA256 */
printk(BIOS_DEBUG, "Initialized RK3288 HW crypto for %u byte SHA256\n",
data_size);
@ -101,12 +101,12 @@ int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size)
{
uint32_t intsts;
write32(HRDMA_ERR | HRDMA_DONE, &crypto->intsts); /* clear interrupts */
writel(HRDMA_ERR | HRDMA_DONE, &crypto->intsts); /* clear interrupts */
/* NOTE: This assumes that the DMA is reading from uncached SRAM. */
write32((uint32_t)buf, &crypto->hrdmas);
write32(size / sizeof(uint32_t), &crypto->hrdmal);
write32(RK_SETBITS(1 << 3), &crypto->ctrl); /* Set HASH_START */
writel((uint32_t)buf, &crypto->hrdmas);
writel(size / sizeof(uint32_t), &crypto->hrdmal);
writel(RK_SETBITS(1 << 3), &crypto->ctrl); /* Set HASH_START */
do {
intsts = read32(&crypto->intsts);
if (intsts & HRDMA_ERR) {

6
src/soc/rockchip/rk3288/timer.c
View File

@ -41,7 +41,7 @@ void timer_monotonic_get(struct mono_time *mt)
void init_timer(void)
{
write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0);
write32(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1);
write32(1, &timer7_ptr->timer_ctrl_reg);
writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count0);
writel(TIMER_LOAD_VAL, &timer7_ptr->timer_load_count1);
writel(1, &timer7_ptr->timer_ctrl_reg);
}

4
src/soc/samsung/exynos5420/dmc_init_ddr3.c
View File

@ -189,8 +189,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
* release pad retention and retain the memory content until the
* initialization is complete.
*/
write32(PAD_RETENTION_DRAM_COREBLK_VAL,
&exynos_power->padret_dram_cblk_opt);
writel(PAD_RETENTION_DRAM_COREBLK_VAL,
&exynos_power->padret_dram_cblk_opt);
do {
ret = read32(&exynos_power->padret_dram_status);
} while (ret != 0x1);

2
src/soc/samsung/exynos5420/dp_lowlevel.c
View File

@ -55,7 +55,7 @@ static inline unsigned long fradl(void *v) {
#define lread32(a) fradl((void *)(a))
#else
#define lwrite32(a,b) write32((unsigned long)(a), (void *)(b))
#define lwrite32(a,b) writel((unsigned long)(a), (void *)(b))
#define lread32(a) read32((void *)(a))
#endif

12
src/soc/samsung/exynos5420/i2c.c
View File

@ -430,7 +430,7 @@ static int hsi2c_senddata(struct hsi2c_regs *regs, const uint8_t *data, int len)
{
while (!hsi2c_check_transfer(regs) && len) {
if (!(read32(&regs->usi_fifo_stat) & Hsi2cTxFifoFull)) {
write32(*data++, &regs->usi_txdata);
writel(*data++, &regs->usi_txdata);
len--;
}
}
@ -452,7 +452,7 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
{
const uint32_t usi_ctl = Hsi2cFuncModeI2c | Hsi2cMaster;
write32(HSI2C_SLV_ADDR_MAS(seg->chip), &regs->i2c_addr);
writel(HSI2C_SLV_ADDR_MAS(seg->chip), &regs->i2c_addr);
/*
* We really only want to stop after this transaction (I think) if the
@ -465,14 +465,14 @@ static int hsi2c_segment(struct i2c_seg *seg, struct hsi2c_regs *regs, int stop)
seg->len | Hsi2cMasterRun | Hsi2cStopAfterTrans;
if (seg->read) {
write32(usi_ctl | Hsi2cRxchon, &regs->usi_ctl);
write32(autoconf | Hsi2cReadWrite, &regs->i2c_auto_conf);
writel(usi_ctl | Hsi2cRxchon, &regs->usi_ctl);
writel(autoconf | Hsi2cReadWrite, &regs->i2c_auto_conf);
if (hsi2c_recvdata(regs, seg->buf, seg->len))
return -1;
} else {
write32(usi_ctl | Hsi2cTxchon, &regs->usi_ctl);
write32(autoconf, &regs->i2c_auto_conf);
writel(usi_ctl | Hsi2cTxchon, &regs->usi_ctl);
writel(autoconf, &regs->i2c_auto_conf);
if (hsi2c_senddata(regs, seg->buf, seg->len))
return -1;