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mb/google/volteer/var/halvor: Correct USB device tree setting 

Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port
therefore disable PCIE/USB3 ports and enable TBT 2.
Follow volteer to set USB2 OC_SKIP.

BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
Eric Lai 2020-08-21 11:09:14 +08:00 committed by Patrick Georgi
parent ae096be00c
commit d234484f31
1 changed files with 7 additions and 6 deletions
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13
src/mainboard/google/volteer/variants/halvor/overridetree.cb
View File

@ -1,23 +1,24 @@
chip soc/intel/tigerlake chip soc/intel/tigerlake
register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # Type-A / Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 0
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC1)" # Type-A / Type-C Port 1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Front Camera
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC2)" # Type-A / Type-C Port 2 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Port 2
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A / Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Port 2
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "SaGv" = "SaGv_Disabled" register "SaGv" = "SaGv_Disabled"
device domain 0 on device domain 0 on
device pci 07.2 on end # TBT_PCIe2
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""