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northbridge/intel/i945/gma.c: Add and use defines for `GMADR` and `GTTADR` 

Change-Id: I0f39b35fbf8e053ba21454a2847d6bb3ac5d2e1c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5923
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Paul Menzel 2014-06-03 00:15:30 +02:00 committed by Kyösti Mälkki
parent 50684638be
commit d235da108b
2 changed files with 4 additions and 2 deletions
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4
src/northbridge/intel/i945/gma.c
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@ -59,8 +59,8 @@ static void gma_func0_init(struct device *dev)
graphics_base = dev->resource_list[2].base + 0x20000; graphics_base = dev->resource_list[2].base + 0x20000;
printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
pci_read_config32(dev, 0x18), pci_read_config32(dev, GMADR),
pci_read_config32(dev, 0x1c) pci_read_config32(dev, GTTADR)
); );
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);

2
src/northbridge/intel/i945/i945.h
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@ -87,6 +87,8 @@
/* Device 0:2.0 PCI configuration space (Graphics Device) */ /* Device 0:2.0 PCI configuration space (Graphics Device) */
#define GMADR 0x18
#define GTTADR 0x1c
#define BSM 0x5c #define BSM 0x5c
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */ #define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */