Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
Creator: Hamish Guthrie <hamish@prodigi.ch> Added AMD GX1 northbridge and cs5530 Southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
parent
4e83d70a43
commit
d24d6993b6
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config chip.h
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object northbridge.o
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struct northbridge_amd_gx1_config
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{
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};
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extern struct chip_operations northbridge_amd_gx1_ops;
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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#include "northbridge.h"
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#include <cpu/amd/gx1def.h>
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#define NORTHBRIDGE_FILE "northbridge.c"
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/*
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*/
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static void optimize_xbus(device_t dev)
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{
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/* Optimise X-Bus performance */
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pci_write_config8(dev, 0x40, 0x1e);
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pci_write_config8(dev, 0x41, 0x52);
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pci_write_config8(dev, 0x43, 0xc1);
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pci_write_config8(dev, 0x44, 0x00);
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}
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static void enable_shadow(device_t dev)
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{
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}
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static void northbridge_init(device_t dev)
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{
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printk_debug("northbridge: %s()\n", __FUNCTION__);
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optimize_xbus(dev);
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enable_shadow(dev);
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}
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static struct device_operations northbridge_operations = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = northbridge_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &northbridge_operations,
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.vendor = PCI_VENDOR_ID_CYRIX,
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.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
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};
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#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
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resource->limit = 0xffffffffULL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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best = new;
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}
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*best_p = best;
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}
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static uint32_t find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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uint32_t tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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return tolm;
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}
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#define FRAMEBUFFERK 4096
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static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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uint32_t pci_tolm;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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unsigned int tomk, tolmk;
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unsigned int ramreg = 0;
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int i, idx;
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unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
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unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
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for(i=0; i<0x20; i+= 0x10) {
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unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
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unsigned int mem_config = *mcreg;
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if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
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continue;
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ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
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}
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tomk = ramreg << 10;
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/* Sort out the framebuffer size */
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tomk -= FRAMEBUFFERK;
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*bcdramtop = ((tomk << 10) - 1);
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*mcgbaseadd = (tomk >> 9);
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printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
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printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
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printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
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/* Compute the top of Low memory */
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tolmk = pci_tolm >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does does not overlap the memory.
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*/
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tolmk = tomk;
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}
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, tolmk);
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}
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_amd_gx1_ops = {
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CHIP_NAME("AMD GX1 Northbridge")
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.enable_dev = enable_dev,
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};
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#ifndef NORTHBRIDGE_INTEL_440BX_H
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#define NORTHBRIDGE_INTEL_440BX_H
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extern unsigned int i440bx_scan_root_bus(device_t root, unsigned int max);
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#endif /* NORTHBRIDGE_INTEL_440BX_H */
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#include <cpu/amd/gx1def.h>
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/*
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This software and ancillary information (herein called SOFTWARE )
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called LinuxBIOS is made available under the terms described
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here. The SOFTWARE has been approved for release with associated
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LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
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been authored by an employee or employees of the University of
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California, operator of the Los Alamos National Laboratory under
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Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
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U.S. Government has rights to use, reproduce, and distribute this
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SOFTWARE. The public may copy, distribute, prepare derivative works
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and publicly display this SOFTWARE without charge, provided that this
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Notice and any statement of authorship are reproduced on all copies.
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Neither the Government nor the University makes any warranty, express
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or implied, or assumes any liability or responsibility for the use of
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this SOFTWARE. If SOFTWARE is modified to produce derivative works,
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such modified SOFTWARE should be clearly marked, so as not to confuse
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it with the version available from LANL.
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*/
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/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
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* rminnich@lanl.gov
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*/
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/* SDRAM initialization for GX1 - translated from Christer Weinigel's
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assembler version into C.
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Hamish Guthrie 10/4/2005 hamish@prodigi.ch
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*/
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#define NUM_REFRESH 8
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#define TEST_DATA1 0x05A5A5A5A
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#define TEST_DATA2 0x0DEADBEEF
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void setGX1Mem(unsigned int addr, unsigned int data)
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{
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writel(data, (volatile void *)addr);
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}
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unsigned int getGX1Mem(unsigned int addr)
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{
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return (unsigned int)readl((const volatile void *)addr);
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}
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void do_refresh(void)
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{
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unsigned int tval, i;
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post_code(0x71);
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i>NUM_REFRESH; i++)
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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post_code(0x72);
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}
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void enable_dimm(void)
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{
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unsigned int tval, i;
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post_code(0x73);
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/* start SDCLCK's */
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
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tval &= ~SDCLKSTRT;
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval |= SDCLKSTRT;
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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/* Unmask SDCLK's */
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL2);
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tval &= ~(SDCLK_MASK | SDCLKOUT_MASK);
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setGX1Mem(GX_BASE + MC_MEM_CNTRL2, tval);
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL2);
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/* Wait for clocks to unmask */
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for(i=0; i<5000; i++)
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outb(0, 0xed);
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/* Refresh memory */
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i<NUM_REFRESH; i++)
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval &= ~RFSHTST;
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/* Start the SDCLK's */
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tval &= ~PROGRAM_SDRAM;
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval |= PROGRAM_SDRAM | 0x00002000; /* Set refresh timing */
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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tval &= ~PROGRAM_SDRAM;
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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/* Refresh memory again */
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tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
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tval |= RFSHTST;
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for(i=0; i>NUM_REFRESH; i++)
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setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
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for(i=0; i<2000; i++)
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outb(0, 0xed);
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post_code(0x74);
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}
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static unsigned int size_dimm(int dimm_shift)
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{
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int bank_cfg = 0x700; /* MC_BANK_CFG for 512M */
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unsigned int offset = 0x10000000; /* Offset 256M */
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int failed_flag = 1;
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do {
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setGX1Mem(0, TEST_DATA1);
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setGX1Mem(offset, TEST_DATA2);
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setGX1Mem(0x100, 0); /* Clear the bus */
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if (getGX1Mem(0) != TEST_DATA1) {
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setGX1Mem(GX_BASE + MC_BANK_CFG,
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getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_SZ << dimm_shift));
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bank_cfg -= 0x100;
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setGX1Mem(GX_BASE + MC_BANK_CFG,
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getGX1Mem(GX_BASE + MC_BANK_CFG) | (bank_cfg << dimm_shift));
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do_refresh();
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offset >>= 1;
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} else {
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failed_flag = 0;
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break;
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}
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} while (bank_cfg >= 0);
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if (failed_flag)
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return (0x0070 << dimm_shift);
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else
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return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift));
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}
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static unsigned int module_banks(int dimm_shift)
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{
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int page_size = 0x800; /* Smallest page = 1K * 2 banks */
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int comp_banks;
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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/* retrieve the page size from the MC register */
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page_size <<= (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
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#if 0
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print_debug(" page_size = ");
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print_debug_hex32(page_size);
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print_debug("\r\n");
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#endif
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comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
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page_size <<= comp_banks;
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setGX1Mem(0, TEST_DATA1);
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setGX1Mem(page_size, TEST_DATA2);
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setGX1Mem(0x100, 0); /* Clear the bus */
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if (getGX1Mem(page_size) != TEST_DATA2) {
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setGX1Mem(GX_BASE + MC_BANK_CFG,
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getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_MOD_BNK << dimm_shift));
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do_refresh();
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}
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
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}
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static unsigned int component_banks(int dimm_shift)
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{
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int page_size = 0x800; /* Smallest page = 1K * 2 banks */
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
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#if 0
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print_debug(" page_size = ");
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print_debug_hex32(page_size);
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print_debug("\r\n");
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#endif
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setGX1Mem(0, TEST_DATA1);
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setGX1Mem(page_size, TEST_DATA2);
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setGX1Mem(0x100, 0); /* Clear the bus */
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if (getGX1Mem(0) != TEST_DATA1) {
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setGX1Mem(GX_BASE + MC_BANK_CFG,
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getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_COMP_BNK << dimm_shift));
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do_refresh();
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}
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#if 0
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print_debug("MC_BANK_CFG = ");
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print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
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print_debug("\r\n");
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#endif
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return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
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}
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static unsigned int page_size(int dimm_shift)
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{
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unsigned int page_test_offset = 0x2000;
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unsigned int temp;
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int page_size_config = 0x40;
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unsigned int probe_config;
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do {
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||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(page_test_offset, TEST_DATA2);
|
||||
setGX1Mem(0x100, 0);
|
||||
temp = getGX1Mem(0);
|
||||
setGX1Mem(0, 0);
|
||||
if(temp == TEST_DATA1) {
|
||||
#if 0
|
||||
print_debug(" Page size Config = ");
|
||||
print_debug_hex32(page_size_config << dimm_shift);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
return(page_size_config << dimm_shift);
|
||||
}
|
||||
|
||||
temp = ~(DIMM_PG_SZ << dimm_shift);
|
||||
|
||||
probe_config = getGX1Mem(GX_BASE + MC_BANK_CFG);
|
||||
probe_config &= temp;
|
||||
|
||||
page_size_config -= 0x10;
|
||||
page_size_config <<= dimm_shift;
|
||||
|
||||
probe_config |= page_size_config;
|
||||
|
||||
page_size_config >>= dimm_shift;
|
||||
|
||||
page_test_offset >>= 1;
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, probe_config);
|
||||
do_refresh();
|
||||
} while (page_size_config >= 0);
|
||||
|
||||
return 0x70;
|
||||
}
|
||||
|
||||
static int dimm_detect(int dimm_shift)
|
||||
{
|
||||
unsigned int test;
|
||||
|
||||
print_debug("Probing for DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(0x100, 0);
|
||||
test = getGX1Mem(0);
|
||||
setGX1Mem(0, 0);
|
||||
|
||||
if (test != TEST_DATA1)
|
||||
return 0;
|
||||
|
||||
print_debug(" Found DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int size_memory(int dimm_shift, unsigned int mem_config)
|
||||
{
|
||||
|
||||
if (!dimm_detect(dimm_shift))
|
||||
return (mem_config);
|
||||
|
||||
mem_config &= (~(DIMM_PG_SZ << dimm_shift));
|
||||
mem_config |= (page_size(dimm_shift));
|
||||
|
||||
print_debug(" Page Size: ");
|
||||
print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
|
||||
print_debug("\r\n");
|
||||
|
||||
/* Now do component banks detection */
|
||||
|
||||
mem_config &= (~(DIMM_COMP_BNK << dimm_shift));
|
||||
mem_config |= (component_banks(dimm_shift));
|
||||
|
||||
print_debug(" Component Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
/* Now do module banks */
|
||||
|
||||
mem_config &= (~(DIMM_MOD_BNK << dimm_shift));
|
||||
mem_config |= (module_banks(dimm_shift));
|
||||
|
||||
print_debug(" Module Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
mem_config &= (~(DIMM_SZ << dimm_shift));
|
||||
mem_config |= (size_dimm(dimm_shift));
|
||||
|
||||
print_debug(" DIMM size: ");
|
||||
print_debug_hex32(1 <<
|
||||
((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
|
||||
print_debug("\r\n");
|
||||
|
||||
return (mem_config);
|
||||
}
|
||||
|
||||
static void sdram_init(void)
|
||||
{
|
||||
unsigned int mem_config = 0x00700070;
|
||||
|
||||
print_debug("Setting up default parameters for memory\r\n");
|
||||
post_code(0x70);
|
||||
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */
|
||||
setGX1Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size
|
||||
0x4000 -- 2 module banks
|
||||
0x1000 -- 4 component banks
|
||||
0x0700 -- DIMM size 512MB
|
||||
0x0040 -- Page Size 16kB */
|
||||
|
||||
enable_dimm();
|
||||
|
||||
print_debug("Sizing memory\r\n");
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
|
||||
do_refresh();
|
||||
mem_config = size_memory(0, mem_config);
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57400070);
|
||||
do_refresh();
|
||||
mem_config = size_memory(16, mem_config);
|
||||
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(mem_config);
|
||||
print_debug("\r\n");
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
|
||||
enable_dimm();
|
||||
post_code(0x7e);
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
device_t d0;
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#config chip.h
|
||||
driver cs5530.o
|
||||
#driver cs5530_pci.o
|
||||
driver cs5530_ide.o
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef _SOUTHBRIDGE_AMD_CS5530
|
||||
#define _SOUTHBRIDGE_AMD_CS5530
|
||||
|
||||
extern struct chip_operations southbridge_amd_cs5530_ops;
|
||||
|
||||
struct southbridge_amd_cs5530_config {
|
||||
/* PCI function enables so the pci scan bus finds the devices */
|
||||
int enable_ide;
|
||||
int enable_nvram;
|
||||
};
|
||||
|
||||
#endif /* _SOUTHBRIDGE_AMD_CS5530 */
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <console/console.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
static void nvram_on(struct device *dev)
|
||||
{
|
||||
#if 0
|
||||
volatile char *flash = (volatile unsigned char *)0xFFFc0000;
|
||||
unsigned char id1, id2;
|
||||
#endif
|
||||
unsigned char reg;
|
||||
|
||||
/* Enable writes to flash at top of memory */
|
||||
pci_write_config8(dev, 0x52, 0xee);
|
||||
|
||||
/* Set positive decode on ROM */
|
||||
/* Also, there is no apparent reason to turn off the devoce on the */
|
||||
/* IDE devices */
|
||||
|
||||
reg = pci_read_config8(dev, 0x5b);
|
||||
reg |= 1 << 5; /* ROM Decode */
|
||||
reg |= 1 << 3; /* Primary IDE decode */
|
||||
reg |= 1 << 4; /* Secondary IDE decode */
|
||||
|
||||
pci_write_config8(dev, 0x5b, reg);
|
||||
|
||||
#if 0 // just to test if the flash is accessible!
|
||||
*(flash + 0x555) = 0xaa;
|
||||
*(flash + 0x2aa) = 0x55;
|
||||
*(flash + 0x555) = 0x90;
|
||||
|
||||
id1 = *(volatile unsigned char *) flash;
|
||||
id2 = *(volatile unsigned char *) (flash + 1);
|
||||
|
||||
*flash = 0xf0;
|
||||
|
||||
printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_init(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5530: %s\n", __FUNCTION__);
|
||||
nvram_on(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
static void dump_south(struct device *dev)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for(i=0; i<256; i+=16) {
|
||||
printk_debug("0x%02x: ", i);
|
||||
for(j=0; j<16; j++)
|
||||
printk_debug("%02x ", pci_read_config8(dev, i+j));
|
||||
printk_debug("\n");
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
static void southbridge_enable(struct device *dev)
|
||||
{
|
||||
printk_spew("%s: dev is %p\n", __FUNCTION__, dev);
|
||||
}
|
||||
|
||||
static void cs5530_pci_dev_enable_resources(device_t dev)
|
||||
{
|
||||
printk_spew("cs5530.c: %s()\n", __FUNCTION__);
|
||||
pci_dev_enable_resources(dev);
|
||||
enable_childrens_resources(dev);
|
||||
}
|
||||
|
||||
static struct device_operations southbridge_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = cs5530_pci_dev_enable_resources,
|
||||
.init = southbridge_init,
|
||||
.enable = southbridge_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
};
|
||||
|
||||
static struct pci_driver cs5530_pci_driver __pci_driver = {
|
||||
.ops = &southbridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5530_LEGACY,
|
||||
};
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#ifndef _CS5530_H
|
||||
#define _CS5530_H
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5530_ide: %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void ide_enable(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5530_ide: %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.enable = ide_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver ide_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
|
||||
};
|
||||
Loading…
Reference in New Issue