i810: Add support for multiple DIMMs, both single-sided and double-sided,
as well as most (all?) combinations thereof. Drop some unused code, the unused row_offset variable, and obsolete comments. Also, fix a typo (thanks to Stefan Reinauer for noticing). This is tested on the MSI MS-6178 with a number of different DIMM combinations and so far all of them worked fine. Signed-off-by: Elia Yehuda <z4ziggy@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Elia Yehuda
Uwe Hermann
parent
4cf5ecf39d
commit
d24fe7e80e
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@ -1,8 +1,9 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
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* Copyright (C) 2008 Elia Yehuda <z4ziggy@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -55,6 +56,22 @@ Macros and definitions.
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#define RAM_COMMAND_MRS 0x6 /* Mode register set */
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#define RAM_COMMAND_CBR 0x7 /* CBR */
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/*
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* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
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* Note that 2 is a value which the DRP should never be programmed to.
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* Some size values appear twice, due to single-sided vs dual-sided banks.
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*/
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static const u16 translate_i82810_to_mb[] = {
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/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
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/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
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};
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/* Size of bank#0 for dual-sided DIMMs */
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static const u8 translate_i82810_to_bank[] = {
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/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
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/* MB */0, 0, 0, 8, 0, 16, 16, 0, 32, 32, 0, 64, 64, 0, 128, 128,
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};
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/*-----------------------------------------------------------------------------
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SDRAM configuration functions.
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-----------------------------------------------------------------------------*/
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@ -62,35 +79,87 @@ SDRAM configuration functions.
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/**
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* Send the specified RAM command to all DIMMs.
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*
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* @param TODO
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* @param TODO
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* @param The RAM command to send to the DIMM(s).
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*/
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static void do_ram_command(uint32_t command, uint32_t addr_offset,
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uint32_t row_offset)
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static void do_ram_command(u8 command)
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{
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uint8_t reg;
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/* TODO: Support for multiple DIMMs. */
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u32 addr, addr_offset;
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u16 dimm_size, dimm_start, dimm_bank;
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u8 reg8, drp;
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int i, caslatency;
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/* Configure the RAM command. */
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reg = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
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reg &= 0x1f; /* Clear bits 7-5. */
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reg |= command << 5;
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pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg);
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reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
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reg8 &= 0x1f; /* Clear bits 7-5. */
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reg8 |= command << 5;
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pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8);
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/* RAM_COMMAND_NORMAL affects only the memory controller and
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doesn't need to be "sent" to the DIMMs. */
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/* if (command == RAM_COMMAND_NORMAL) return; */
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/*
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* RAM_COMMAND_NORMAL affects only the memory controller and
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* doesn't need to be "sent" to the DIMMs.
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*/
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if (command == RAM_COMMAND_NORMAL)
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return;
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dimm_start = 0;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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/*
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* Calculate the address offset where we need to "send" the
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* DIMM command to. For most commands the offset is 0, only
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* RAM_COMMAND_MRS needs special values, see below.
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* The final address offset bits depend on three things:
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*
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* (1) Some hardcoded values specified in the datasheet.
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* (2) Which CAS latency we will use/set. This is the SMAA[4]
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* bit, which is 1 for CL3, and 0 for CL2. The bitstring
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* so far has the form '00000001X1010', X being SMAA[4].
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* (3) The DIMM to which we want to send the command. For
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* DIMM0 no special handling is needed, but for DIMM1 we
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* must invert the four bits SMAA[7:4] (see datasheet).
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*
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* Finally, the bitstring has to be shifted 3 bits to the left.
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* See i810 datasheet pages 43, 85, and 86 for details.
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*/
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addr_offset = 0;
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caslatency = 3; /* TODO: Dynamically get CAS latency later. */
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if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 3)
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addr_offset = 0x1d0; /* DIMM0, CL3, 0000111010000 */
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if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 3)
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addr_offset = 0x650; /* DIMM1, CL3, 0011001010000 */
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if (i == 0 && command == RAM_COMMAND_MRS && caslatency == 2)
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addr_offset = 0x150; /* DIMM0, CL2, 0000101010000 */
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if (i == 1 && command == RAM_COMMAND_MRS && caslatency == 2)
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addr_offset = 0x1a0; /* DIMM1, CL2, 0000110100000 */
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drp = pci_read_config8(PCI_DEV(0, 0, 0), DRP);
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drp = (drp >> (i * 4)) & 0x0f;
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dimm_size = translate_i82810_to_mb[drp];
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addr = (dimm_start * 1024 * 1024) + addr_offset;
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if (dimm_size) {
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG_HEX8(reg);
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PRINT_DEBUG_HEX8(reg8);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
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PRINT_DEBUG_HEX32(addr);
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PRINT_DEBUG("\r\n");
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/* Read from (DIMM start address + addr_offset). */
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read32(0 + addr_offset); //first offset is always 0
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read32(row_offset + addr_offset);
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read32(addr);
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}
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dimm_bank = translate_i82810_to_bank[drp];
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addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
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if (dimm_bank) {
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG_HEX8(reg8);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX32(addr);
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PRINT_DEBUG("\r\n");
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read32(addr);
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}
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dimm_start += dimm_size;
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}
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}
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/*-----------------------------------------------------------------------------
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@ -100,7 +169,7 @@ DIMM-independant configuration functions.
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/*
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* Set DRP - DRAM Row Population Register (Device 0).
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*/
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static void spd_set_dram_size(uint32_t row_offset)
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static void spd_set_dram_size(void)
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{
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/* The variables drp and dimm_size have to be ints since all the
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* SMBus-related functions return ints, and its just easier this way.
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@ -137,36 +206,6 @@ static void spd_set_dram_size(uint32_t row_offset)
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dimm_size = 32;
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}
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/* Set the row offset, in KBytes (should this be
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* Kbits?). Note that this offset is the start of the
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* next row.
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*/
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row_offset = (dimm_size * 4 * 1024);
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/* This is the way I was doing this, it's provided
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* mainly as an alternative to the "new" way.
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*/
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#if 0
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/* 8MB */
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if (dimm_size == 0x2)
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dimm_size = 0x1;
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/* 16MB */
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else if (dimm_size == 0x4)
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dimm_size = 0x4;
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/* 32MB */
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else if (dimm_size == 0x8)
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dimm_size = 0x7;
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/* 64 MB */
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else if (dimm_size == 0x10)
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dimm_size = 0xa;
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/* 128 MB */
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else if (dimm_size == 0x20)
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dimm_size = 0xd;
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else
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print_debug("Ram Size not supported\r\n");
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#endif
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/* This array is provided in raminit.h, because it got
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* extremely messy. The above way is cleaner, but
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* doesn't support any asymetrical/odd configurations.
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@ -212,7 +251,7 @@ static void set_dram_timing(void)
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/*
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* TODO: BUFF_SC needs to be set according to the DRAM tech (x8, x16,
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* or x32), but the datasheet doesn't list all the detaisl. Currently, it
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* or x32), but the datasheet doesn't list all the details. Currently, it
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* needs to be pulled from the output of 'lspci -xxx Rx92'.
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*
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* Common results (tested on actual hardware) are:
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@ -246,9 +285,6 @@ static void set_dram_buffer_strength(void)
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Public interface.
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-----------------------------------------------------------------------------*/
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/**
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* TODO.
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*/
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static void sdram_set_registers(void)
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{
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unsigned long val;
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@ -292,16 +328,10 @@ static void sdram_set_registers(void)
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//pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
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}
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/**
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* TODO.
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*/
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static void sdram_set_spd_registers(void)
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{
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/* spd_set_dram_size() moved into sdram_enable() to prevent having
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* to pass a variable between here and there.
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*/
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spd_set_dram_size();
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set_dram_buffer_strength();
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set_dram_timing();
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}
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@ -312,41 +342,31 @@ static void sdram_enable(void)
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{
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int i;
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/* Todo: this will currently work with either one dual sided or two
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* single sided DIMMs. Needs to work with 2 dual sided DIMMs in the
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* long run.
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*/
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uint32_t row_offset;
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spd_set_dram_size(row_offset);
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/* 1. Apply NOP. */
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PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
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do_ram_command(RAM_COMMAND_NOP, 0, row_offset);
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do_ram_command(RAM_COMMAND_NOP);
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udelay(200);
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/* 2. Precharge all. Wait tRP. */
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PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
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do_ram_command(RAM_COMMAND_PRECHARGE, 0, row_offset);
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do_ram_command(RAM_COMMAND_PRECHARGE);
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udelay(1);
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/* 3. Perform 8 refresh cycles. Wait tRC each time. */
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PRINT_DEBUG("RAM Enable 3: CBR\r\n");
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do_ram_command(RAM_COMMAND_CBR, 0, row_offset);
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for (i = 0; i < 8; i++) {
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read32(0);
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read32(row_offset);
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do_ram_command(RAM_COMMAND_CBR);
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udelay(1);
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}
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/* 4. Mode register set. Wait two memory cycles. */
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PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
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do_ram_command(RAM_COMMAND_MRS, 0x1d0, row_offset);
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do_ram_command(RAM_COMMAND_MRS);
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udelay(2);
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/* 5. Normal operation (enables refresh) */
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PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
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do_ram_command(RAM_COMMAND_NORMAL, 0, row_offset);
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do_ram_command(RAM_COMMAND_NORMAL);
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udelay(1);
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PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
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