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mb/intel/tglrvp: Enable SATA 

Enable both SATA ports for TGLRVP.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38505
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-01-21 21:54:14 -08:00 committed by Subrata Banik
parent 815d96a975
commit d250063c09
1 changed files with 5 additions and 1 deletions
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6
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -45,6 +45,10 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8" register "PcieClkSrcUsage[3]" = "0x8"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SerialIoI2cMode" = "{ register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci,
@ -122,7 +126,7 @@ chip soc/intel/tigerlake
device pci 16.3 off end # CSME 0xA0E3 device pci 16.3 off end # CSME 0xA0E3
device pci 16.4 off end # HECI3 0xA0E4 device pci 16.4 off end # HECI3 0xA0E4
device pci 16.5 off end # HECI4 0xA0E5 device pci 16.5 off end # HECI4 0xA0E5
device pci 17.0 off end # SATA 0xA0D3 device pci 17.0 on end # SATA 0xA0D3
device pci 19.0 off end # I2C4 0xA0C5 device pci 19.0 off end # I2C4 0xA0C5
device pci 19.1 on end # I2C5 0xA0C6 device pci 19.1 on end # I2C5 0xA0C6
device pci 19.2 on end # UART2 0xA0C7 device pci 19.2 on end # UART2 0xA0C7