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mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree

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The devicetree was synced incorrectly with respect to the function
disable register set in romstage.

Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30711
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-01-07 15:30:21 +01:00 committed by Nico Huber
parent 458297c8ba
commit d25109905a
3 changed files with 4 additions and 4 deletions
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2
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
View file

@ -61,7 +61,7 @@ chip northbridge/intel/x4x # Northbridge
subsystemid 0x1458 0xe000
end
end
device pci 1c.2 on end # PCIe 3
device pci 1c.2 off end # PCIe 3
device pci 1c.3 off end # PCIe 4
device pci 1c.4 off end # PCIe 5
device pci 1c.5 off end # PCIe 6

2
src/mainboard/intel/d945gclf/devicetree.cb
View file

@ -64,7 +64,7 @@ chip northbridge/intel/i945
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.3 off end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
device pci 1e.2 off end # AC'97 Audio

4
src/mainboard/roda/rk886ex/devicetree.cb
View file

@ -63,7 +63,7 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
device pci 1b.0 on end # High Definition Audio
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 on end # PCIe port 1
device pci 1c.1 off end # PCIe port 2
device pci 1c.2 off end # PCIe port 3
@ -84,7 +84,7 @@ chip northbridge/intel/i945
device pci 3.3 off end # smartcard
end
end # PCI bridge
device pci 1e.2 off end # AC'97 Audio
device pci 1e.2 on end # AC'97 Audio
device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47n227