mb/hp: Enable additional ports at WWAN slot for Elitebooks
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -42,14 +42,14 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 0, 2 }, /* bluetooth */
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{ 0, 0, 3 },
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{ 0, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 3 }, /* smartcard */
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{ 1, 1, 4 },
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{ 1, 1, 4 },
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{ 1, 1, 4 },
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{ 1, 1, 4 }, /* mainboard USB 2.0 */
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{ 1, 0, 5 },
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{ 1, 0, 5 }, /* camera */
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{ 0, 0, 5 },
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{ 0, 0, 5 },
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{ 1, 0, 6 },
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{ 1, 0, 6 }, /* WWAN */
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{ 0, 0, 6 },
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{ 0, 0, 6 },
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};
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};
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@ -106,7 +106,7 @@ chip northbridge/intel/sandybridge
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end
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end
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device pci 1c.5 off # PCIe Port #6
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device pci 1c.5 off # PCIe Port #6
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end
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end
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device pci 1c.6 off # PCIe Port #7
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device pci 1c.6 on # PCIe Port #7, WWAN
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end
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end
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device pci 1c.7 off # PCIe Port #8
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device pci 1c.7 off # PCIe Port #8
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end
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end
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@ -67,6 +67,7 @@ chip northbridge/intel/sandybridge
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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# HDD(0), ODD(1), docking(3,5), eSATA(4)
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register "sata_port_map" = "0x3b"
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register "sata_port_map" = "0x3b"
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register "spi_uvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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@ -107,7 +108,7 @@ chip northbridge/intel/sandybridge
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end
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end
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device pci 1c.5 off # PCIe Port #6
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device pci 1c.5 off # PCIe Port #6
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end
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end
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device pci 1c.6 off # PCIe Port #7
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device pci 1c.6 on # PCIe Port #7, WWAN
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end
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end
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device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller
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device pci 1c.7 on # PCIe Port #8, NEC USB 3.0 Host Controller
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subsystemid 0x103c 0x161c
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subsystemid 0x103c 0x161c
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@ -43,20 +43,20 @@ void mainboard_rcba_config(void)
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}
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 0 },
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{ 1, 1, 0 }, /* USB0, eSATA */
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{ 1, 0, 0 },
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{ 1, 0, 0 }, /* USB charger */
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{ 0, 1, 1 },
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{ 0, 1, 1 },
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{ 1, 1, 1 },
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{ 1, 1, 1 }, /* camera */
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{ 1, 0, 2 },
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{ 1, 0, 2 }, /* USB4 expresscard */
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{ 1, 0, 2 },
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{ 1, 0, 2 }, /* bluetooth */
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{ 0, 0, 3 },
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{ 0, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 3 }, /* smartcard */
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{ 1, 1, 4 },
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{ 1, 1, 4 }, /* fingerprint */
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{ 1, 1, 4 },
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{ 1, 1, 4 }, /* WWAN */
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{ 1, 0, 5 },
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{ 1, 0, 5 }, /* CONN */
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{ 1, 0, 5 },
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{ 1, 0, 5 }, /* docking */
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{ 1, 0, 6 },
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{ 1, 0, 6 }, /* CONN */
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{ 1, 0, 6 },
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{ 1, 0, 6 }, /* docking */
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};
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};
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void mainboard_early_init(int s3resume)
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void mainboard_early_init(int s3resume)
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@ -68,7 +68,8 @@ chip northbridge/intel/sandybridge
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3b"
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# HDD(0), ODD(1), mSATA(2), eSATA(4)
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register "sata_port_map" = "0x3f"
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register "superspeed_capable_ports" = "0x0000000f"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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register "xhci_switchable_ports" = "0x0000000f"
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