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Coding style: punctuation cleanup [1/2]. 

Clean up superfluous line terminators.

Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Idwer Vollering 2013-12-22 21:38:18 +00:00 committed by Alexandru Gagniuc
parent c6c8cb7f79
commit d26da9c8f0
21 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/i2c/rtd2132/rtd2132.c
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@ -181,7 +181,7 @@ static void rtd2132_lvds_swap(device_t dev,
if (cfg->lvds_swap & RTD2132_LVDS_SWAP_CFG_DUAL)
swap_value |= RTD2132_LVDS_SWAP_DUAL;
printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);;
printk(BIOS_INFO, "RTD2132: LVDS Swap 0x%02x\n", swap_value);
rtd2132_write_reg(dev, RTD2132_COMMAND_LVDS_SWAP, swap_value);
}

4
src/ec/quanta/it8518/ec.c
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@ -40,7 +40,7 @@ static int input_buffer_empty(u16 status_reg)
u32 timeout;
for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF);
timeout--) {
udelay(1000);;
udelay(1000);
}
if (!timeout) {
@ -56,7 +56,7 @@ static int output_buffer_full(u16 status_reg)
u32 timeout;
for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg)
& KBD_OBF) == 0); timeout--) {
udelay(1000);;
udelay(1000);
}
if (!timeout) {

2
src/lib/cbfs.c
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@ -312,7 +312,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name)
void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
struct cbfs_media *media,
size_t offset, size_t count) {
void *address = buffer->buffer + buffer->allocated;;
void *address = buffer->buffer + buffer->allocated;
DEBUG("simple_buffer_map(offset=%zd, count=%zd): "
"allocated=%zd, size=%zd, last_allocate=%zd\n",
offset, count, buffer->allocated, buffer->size,

2
src/lib/dynamic_cbmem.c
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@ -294,7 +294,7 @@ const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64)
{
struct cbmem_root *root;
const struct cbmem_entry *entry;
unsigned long base;;
unsigned long base;
u32 size;
u32 aligned_size;

2
src/mainboard/google/bolt/smihandler.c
View File

@ -149,7 +149,7 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

2
src/mainboard/google/falco/smihandler.c
View File

@ -166,7 +166,7 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

2
src/mainboard/google/link/mainboard_smi.c
View File

@ -153,7 +153,7 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);
break;
}
return 0;

2
src/mainboard/google/parrot/chromeos.c
View File

@ -72,7 +72,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Lid switch GPIO active high (open). */
gpios->gpios[3].port = 15;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = ((gp_lvl >> 15) & 1);;
gpios->gpios[3].value = ((gp_lvl >> 15) & 1);
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */

2
src/mainboard/google/peppy/smihandler.c
View File

@ -163,7 +163,7 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

2
src/mainboard/google/slippy/smihandler.c
View File

@ -150,7 +150,7 @@ int mainboard_smi_apmc(u8 apmc)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0);
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);;
google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
break;
}
return 0;

2
src/northbridge/amd/amdmct/wrappers/mcti_d.c
View File

@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index)
//val = 200; /* 200MHz(DDR400) */
//val = 266; /* 266MHz(DDR533) */
//val = 333; /* 333MHz(DDR667) */
val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */
val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */
break;
case NV_ECC_CAP:
#if SYSTEM_TYPE == SERVER

4
src/northbridge/intel/i5000/raminit.c
View File

@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
}
printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);
printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);
pci_write_config16(dev16, I5000_MIR0, mir0);
pci_write_config16(dev16, I5000_MIR1, mir1);

2
src/northbridge/via/vx800/detection.c
View File

@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr)
DramAttr->DimmNumChB++;
DramAttr->LoadNumChB =
(u8) (DramAttr->LoadNumChB * LoadNum *
RankNum);;
RankNum);
}
RankNum |= 1; /* Set rank map. */
DramAttr->RankPresentMap |= (RankNum << (Sockets * 2));

2
src/northbridge/via/vx800/freq_setting.c
View File

@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr)
Data = (u8) ((Data & 0xf8) | 6);
break;
default:
Data = (u8) ((Data & 0xf8) | 1);;
Data = (u8) ((Data & 0xf8) | 1);
}
pci_write_config8(MEMCTRL, 0x90, Data);

4
src/northbridge/via/vx900/raminit_ddr3.c
View File

@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms,
} else {
/* Otherwise, everything is held in the first bank */
ranks->phys_rank_size_mb[i << 1] = size;
ranks->phys_rank_size_mb[(i << 1) | 1] = 0;;
ranks->phys_rank_size_mb[(i << 1) | 1] = 0;
}
}
}
@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq,
{
/* Same timeout reasoning as in receive delays */
size_t n_tries = 0;
int dq_tries = 0, dqs_tries = 0;;
int dq_tries = 0, dqs_tries = 0;
const size_t max_tries = 100;
for (;;) {
if (n_tries++ >= max_tries) {

2
src/southbridge/amd/cimx/sb800/spi.c
View File

@ -117,7 +117,7 @@ static void ImcSleep(void)
static void ImcWakeup(void)
{
u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */
u8 reg0_val = 0;; /* clear response register */
u8 reg0_val = 0; /* clear response register */
u8 reg1_val = 0xB5; /* release ownership flag */
WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val);

2
src/southbridge/amd/sb700/sm.c
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@ -151,7 +151,7 @@ static void sm_init(device_t dev)
pm_iowrite(0x55, byte);
byte = pm_ioread(0xD7);
byte |= 1 << 6 | 1 << 1;;
byte |= 1 << 6 | 1 << 1;
pm_iowrite(0xD7, byte);
/* 2.15 */

2
src/southbridge/amd/sb800/early_setup.c
View File

@ -276,7 +276,7 @@ void sb800_pci_port80(void)
pci_write_config8(dev, 0x04, byte);
/* LPC controller */
dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
byte = pci_read_config8(dev, 0x4A);
byte &= ~(1 << 5); /* disable lpc port 80 */

2
src/southbridge/intel/i82371eb/fadt.c
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@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;

2
src/southbridge/nvidia/mcp55/fadt.c
View File

@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;

2
src/southbridge/via/vt8237r/fadt.c
View File

@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;