cx700 int15 handler rework. Int15 handler needs to provide the
correct ram clock to the vga bios or there be dragons. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
e08c29e0e7
commit
d2759fff55
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@ -36,237 +36,11 @@
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#define SCRATCH_DRAM_256M_BIT 0xee
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#define SCRATCH_FLAGS 0xef
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static const u8 Reg_Val[] = {
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/* REG, VALUE */
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0x70, 0x33,
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0x71, 0x11,
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0x72, 0x33,
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0x73, 0x11,
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0x74, 0x20,
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0x75, 0x2e,
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0x76, 0x64,
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0x77, 0x00,
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0x78, 0x44,
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0x79, 0xaa,
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0x7a, 0x33,
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0x7b, 0xaa,
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0x7c, 0x00,
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0x7e, 0x33,
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0x7f, 0x33,
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0x80, 0x44,
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0x81, 0x44,
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0x82, 0x44,
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0x83, 0x02,
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0x50, 0x88,
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0x51, 0x7b,
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0x52, 0x6f,
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0x53, 0x88,
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0x54, 0x0e,
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0x55, 0x00,
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0x56, 0x00,
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0x59, 0x00,
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0x5d, 0x72,
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0x5e, 0x88,
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0x5f, 0xc7,
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0x68, 0x01,
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};
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#define DDRII_666 0x5
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#define DDRII_533 0x4
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#define DDRII_400 0x3
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#define DDRII_333 0x2
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#define DDRII_266 0x1
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#define DDRII_200 0x0
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/* Host registers initial value */
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static const u8 Host_Reg_Val[] = {
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/* REG, VALUE */
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0x60, 0xff,
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0x61, 0xff,
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0x62, 0x0f,
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0x63, 0xff,
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0x64, 0xff,
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0x65, 0x0f,
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0x66, 0xff,
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0x67, 0x30,
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};
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static const u8 Mem_Reg_Init[] = {
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/* REG, AND, OR */
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0x50, 0x11, 0x66,
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0x51, 0x11, 0x66,
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0x52, 0x00, 0x11,
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0x53, 0x00, 0x0f,
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0x54, 0x00, 0x00,
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0x55, 0x00, 0x00,
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0x56, 0x00, 0x00,
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0x57, 0x00, 0x00,
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0x60, 0x00, 0x00,
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0x62, 0xf7, 0x08,
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0x65, 0x00, 0xd9,
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0x66, 0x00, 0x80,
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0x67, 0x00, 0x50, /* OR 0x00 ?? */
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0x69, 0xf0, 0x00,
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0x6a, 0x00, 0x00,
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0x6d, 0xcf, 0xc0,
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0x6e, 0xff, 0x80,
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0x75, 0x0f, 0x40,
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0x77, 0x00, 0x00,
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0x80, 0x00, 0x00,
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0x81, 0x00, 0x00,
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0x82, 0x00, 0x00,
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0x83, 0x00, 0x00,
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0x84, 0x00, 0x00,
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0x85, 0x00, 0x00,
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0x86, 0xff, 0x2c, /* OR 0x28 if we don't want enable top 1M SM memory */
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0x40, 0x00, 0x00,
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0x7c, 0x00, 0x00,
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0x7e, 0x00, 0x00,
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0xa4, 0xfe, 0x00,
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0xb0, 0x7f, 0x80,
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0xb1, 0x00, 0xaa,
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0xb4, 0xfd, 0x02,
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0xb8, 0xfe, 0x00,
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};
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static const u8 Dram_Driving_ODT_CTRL[] = {
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/* REG, VALUE */
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0xd6, 0xa8,
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0xd4, 0x80,
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0xd0, 0x88,
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0xd3, 0x01,
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0xd8, 0x00,
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0xda, 0x80,
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};
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#define Rank0_ODT 0x00
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#define Rank1_ODT 0x01
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#define Rank2_ODT 0x02
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#define Rank3_ODT 0x03
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#define NA_ODT 0x00
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#define NB_ODT_75ohm 0x00
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#define NB_ODT_150ohm 0x01
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#define DDR2_ODT_75ohm 0x20
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#define DDR2_ODT_150ohm 0x40
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static const u8 ODT_TBL[] = {
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/* RankMap, ODT Control Bits, DRAM & NB ODT setting */
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0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
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0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
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0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
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0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
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0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
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0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
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0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
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0x0f, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
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};
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static const u8 DQS_DQ_TBL[] = {
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/* RxE0: DRAM Timing DQS */
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/* RxE2: DRAM Timing DQ */
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/* RxE0, RxE2 */
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0xee, 0xba,
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0xee, 0xba,
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0xcc, 0xba,
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0xcc, 0xba,
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};
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static const u8 Duty_Control_DDR2[] = {
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/* RxEC, RxED, RxEE, RXEF */
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/* DDRII533 1~2 rank, DDRII400 */
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0x84, 0x10, 0x00, 0x10,
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/* DDRII533 3~4 rank */
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0x44, 0x10, 0x00, 0x10,
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};
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static const u8 ChA_Clk_Phase_DDR2_Table[] = {
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/* Rx91, Rx92, Rx93 */
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/* DDRII533 1 rank */
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0x04, 0x05, 0x06,
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/* DDRII533 2~4 rank */
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0x04, 0x05, 0x05,
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/* DDRII400 */
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0x02, 0x04, 0x04,
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};
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static const u8 DQ_DQS_Table[] = {
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/* REG, VALUE */
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/* DRAM DQ/DQS Output Delay Control */
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0xdc, 0x65,
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0xdd, 0x01,
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0xde, 0xc0,
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/* DRAM DQ/DQS input Capture Control */
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0x78, 0x83,
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0x79, 0x83,
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0x7a, 0x00,
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};
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static const u8 DQSOChA_DDR2_Driving_Table[] = {
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/* Rx70, Rx71 */
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/* DDRII533 1~2 rank */
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0x00, 0x01,
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/* DDRII533 3~4 rank */
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0x03, 0x00,
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/* DDRII400 1~2 rank */
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0x00, 0x04,
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/* DDRII400 3~4 rank */
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0x00, 0x01,
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};
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/************************************************************************/
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/* Chipset Performance UP and other setting after DRAM Sizing Registers */
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/************************************************************************/
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static const u8 Dram_Table[] = {
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/* REG, AND, OR */
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0x60, 0xff, 0x03,
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0x66, 0xcf, 0x80,
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0x68, 0x00, 0x00,
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0x69, 0xfd, 0x03,
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0x6e, 0xff, 0x01,
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0x95, 0xff, 0x40,
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};
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static const u8 Host_Table[] = {
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/* REG, AND, OR */
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0x51, 0x81, 0x7a,
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0x55, 0xff, 0x06,
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0x5e, 0x00, 0x88,
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0x5d, 0xff, 0xb2,
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};
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static const u8 Init_Rank_Reg_Table[] = {
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/* Rank Ending Address Registers */
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0x40, 0x41, 0x42, 0x43,
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/* Rank Beginning Address Registers */
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0x48, 0x49, 0x4a, 0x4b,
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/* Physical-to-Virtual Rank Mapping Registers */
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0x54, 0x55,
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};
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static const u16 DDR2_MRS_table[] = {
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/* CL: 2, 3, 4, 5 */
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0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */
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0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */
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};
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#define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12))
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#define MRS_DDR2_TWR3 ((0 << 15) | (1 << 20) | (0 << 12))
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#define MRS_DDR2_TWR4 ((0 << 15) | (1 << 20) | (1 << 12))
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#define MRS_DDR2_TWR5 ((1 << 15) | (0 << 20) | (0 << 12))
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static const u32 DDR2_Twr_table[] = {
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MRS_DDR2_TWR2,
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MRS_DDR2_TWR3,
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MRS_DDR2_TWR4,
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MRS_DDR2_TWR5,
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};
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static const u8 DQSI_Rate_Table[] = {
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8, /* DDRII 200 */
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8, /* DDRII 266 */
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8, /* DDRII 333 */
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7, /* DDRII 400 */
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8, /* DDRII 533 */
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8, /* DDRII 666 */
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};
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static const u8 REFC_Table[] = {
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0x65, 0x32, /* DDRII 100 */
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0x86, 0x43, /* DDRII 266 */
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0xa8, 0x54, /* DDRII 333 */
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0xca, 0x65, /* DDRII 400 */
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0xca, 0x86, /* DDRII 533 */
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0xca, 0xa8, /* DDRII 666 */
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};
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@ -30,6 +30,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <arch/interrupt.h>
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#include "cx700_registers.h"
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#include "chip.h"
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#include "northbridge.h"
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@ -45,34 +46,79 @@
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static int via_cx700_int15_handler(struct eregs *regs)
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{
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int res=-1;
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u8 mem_speed;
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#define MEMORY_SPEED_66MHZ (0 << 4)
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#define MEMORY_SPEED_100MHZ (1 << 4)
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#define MEMORY_SPEED_133MHZ (1 << 4)
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#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200
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#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266
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#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333
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#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400
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#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533
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#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667
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const u8 memory_mapping[6] = {
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MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ,
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MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ,
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MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ
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};
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printk(BIOS_DEBUG, "via_cx700_int15_handler\n");
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switch(regs->eax & 0xffff) {
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case 0x5f19:
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break;
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case 0x5f18:
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regs->eax=0x5f;
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regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory
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regs->ecx=0x060;
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res=0;
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break;
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case 0x5f00:
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regs->eax = 0x8600;
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break;
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case 0x5f01:
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regs->eax = 0x5f;
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regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
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case 0x5f00: /* VGA POST Initialization Signal */
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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res = 0;
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break;
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case 0x5f02:
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regs->eax=0x5f;
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regs->ebx= (regs->ebx & 0xffff0000) | 2;
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regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
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regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default
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case 0x5f01: /* Software Panel Type Configuration */
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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// panel type = 2 = 1024 * 768
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regs->ecx = (regs->ecx & 0xffffff00 ) | 2;
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res = 0;
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break;
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case 0x5f27: /* Boot Device Selection */
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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regs->ebx = 0x00000000; // 0 -> default
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regs->ecx = 0x00000000; // 0 -> default
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// TV Layout - default
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regs->edx = (regs->edx & 0xffffff00) | 0;
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res=0;
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break;
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case 0x5f0f:
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regs->eax=0x860f;
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case 0x5f0b: /* Get Expansion Setting */
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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regs->ecx = regs->ecx & 0xffffff00; // non-expansion
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// regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion
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res=0;
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break;
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case 0x5f0f: /* VGA Post Completion */
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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res=0;
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break;
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case 0x5f18:
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regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
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#define UMA_SIZE_8MB (3 << 0)
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#define UMA_SIZE_16MB (4 << 0)
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#define UMA_SIZE_32MB (5 << 0)
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regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB;
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mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ);
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if (mem_speed > 5)
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mem_speed = 5;
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regs->ebx |= memory_mapping[mem_speed]; break;
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res=0;
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break;
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default:
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printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
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regs->eax & 0xffff);
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@ -39,13 +39,6 @@
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#define HOSTCTRL PCI_DEV(0, 0, 2)
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#define MEMCTRL PCI_DEV(0, 0, 3)
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#define DDRII_666 0x5
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#define DDRII_533 0x4
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#define DDRII_400 0x3
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#define DDRII_333 0x2
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#define DDRII_266 0x1
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#define DDRII_200 0x0
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#define OHM_150 1
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#ifdef MEM_WIDTH_32BIT_MODE
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@ -114,6 +107,240 @@
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} \
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}
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static const u8 Reg_Val[] = {
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/* REG, VALUE */
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0x70, 0x33,
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0x71, 0x11,
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0x72, 0x33,
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0x73, 0x11,
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0x74, 0x20,
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0x75, 0x2e,
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0x76, 0x64,
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0x77, 0x00,
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0x78, 0x44,
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0x79, 0xaa,
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0x7a, 0x33,
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0x7b, 0xaa,
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0x7c, 0x00,
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0x7e, 0x33,
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0x7f, 0x33,
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0x80, 0x44,
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0x81, 0x44,
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0x82, 0x44,
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0x83, 0x02,
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0x50, 0x88,
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0x51, 0x7b,
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0x52, 0x6f,
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0x53, 0x88,
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0x54, 0x0e,
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0x55, 0x00,
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0x56, 0x00,
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0x59, 0x00,
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0x5d, 0x72,
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0x5e, 0x88,
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0x5f, 0xc7,
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0x68, 0x01,
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};
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/* Host registers initial value */
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static const u8 Host_Reg_Val[] = {
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/* REG, VALUE */
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0x60, 0xff,
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0x61, 0xff,
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0x62, 0x0f,
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0x63, 0xff,
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0x64, 0xff,
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0x65, 0x0f,
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||||
0x66, 0xff,
|
||||
0x67, 0x30,
|
||||
};
|
||||
|
||||
static const u8 Mem_Reg_Init[] = {
|
||||
/* REG, AND, OR */
|
||||
0x50, 0x11, 0x66,
|
||||
0x51, 0x11, 0x66,
|
||||
0x52, 0x00, 0x11,
|
||||
0x53, 0x00, 0x0f,
|
||||
0x54, 0x00, 0x00,
|
||||
0x55, 0x00, 0x00,
|
||||
0x56, 0x00, 0x00,
|
||||
0x57, 0x00, 0x00,
|
||||
0x60, 0x00, 0x00,
|
||||
0x62, 0xf7, 0x08,
|
||||
0x65, 0x00, 0xd9,
|
||||
0x66, 0x00, 0x80,
|
||||
0x67, 0x00, 0x50, /* OR 0x00 ?? */
|
||||
0x69, 0xf0, 0x00,
|
||||
0x6a, 0x00, 0x00,
|
||||
0x6d, 0xcf, 0xc0,
|
||||
0x6e, 0xff, 0x80,
|
||||
0x75, 0x0f, 0x40,
|
||||
0x77, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00,
|
||||
0x81, 0x00, 0x00,
|
||||
0x82, 0x00, 0x00,
|
||||
0x83, 0x00, 0x00,
|
||||
0x84, 0x00, 0x00,
|
||||
0x85, 0x00, 0x00,
|
||||
0x86, 0xff, 0x2c, /* OR 0x28 if we don't want enable top 1M SM memory */
|
||||
0x40, 0x00, 0x00,
|
||||
0x7c, 0x00, 0x00,
|
||||
0x7e, 0x00, 0x00,
|
||||
0xa4, 0xfe, 0x00,
|
||||
0xb0, 0x7f, 0x80,
|
||||
0xb1, 0x00, 0xaa,
|
||||
0xb4, 0xfd, 0x02,
|
||||
0xb8, 0xfe, 0x00,
|
||||
};
|
||||
|
||||
static const u8 Dram_Driving_ODT_CTRL[] = {
|
||||
/* REG, VALUE */
|
||||
0xd6, 0xa8,
|
||||
0xd4, 0x80,
|
||||
0xd0, 0x88,
|
||||
0xd3, 0x01,
|
||||
0xd8, 0x00,
|
||||
0xda, 0x80,
|
||||
};
|
||||
|
||||
#define Rank0_ODT 0x00
|
||||
#define Rank1_ODT 0x01
|
||||
#define Rank2_ODT 0x02
|
||||
#define Rank3_ODT 0x03
|
||||
#define NA_ODT 0x00
|
||||
#define NB_ODT_75ohm 0x00
|
||||
#define NB_ODT_150ohm 0x01
|
||||
#define DDR2_ODT_75ohm 0x20
|
||||
#define DDR2_ODT_150ohm 0x40
|
||||
|
||||
static const u8 ODT_TBL[] = {
|
||||
/* RankMap, ODT Control Bits, DRAM & NB ODT setting */
|
||||
0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
|
||||
0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
|
||||
0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
|
||||
0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
|
||||
0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
|
||||
0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
|
||||
0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
|
||||
0x0f, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
|
||||
};
|
||||
|
||||
static const u8 DQS_DQ_TBL[] = {
|
||||
/* RxE0: DRAM Timing DQS */
|
||||
/* RxE2: DRAM Timing DQ */
|
||||
/* RxE0, RxE2 */
|
||||
0xee, 0xba,
|
||||
0xee, 0xba,
|
||||
0xcc, 0xba,
|
||||
0xcc, 0xba,
|
||||
};
|
||||
|
||||
static const u8 Duty_Control_DDR2[] = {
|
||||
/* RxEC, RxED, RxEE, RXEF */
|
||||
/* DDRII533 1~2 rank, DDRII400 */
|
||||
0x84, 0x10, 0x00, 0x10,
|
||||
/* DDRII533 3~4 rank */
|
||||
0x44, 0x10, 0x00, 0x10,
|
||||
};
|
||||
|
||||
static const u8 ChA_Clk_Phase_DDR2_Table[] = {
|
||||
/* Rx91, Rx92, Rx93 */
|
||||
/* DDRII533 1 rank */
|
||||
0x04, 0x05, 0x06,
|
||||
/* DDRII533 2~4 rank */
|
||||
0x04, 0x05, 0x05,
|
||||
/* DDRII400 */
|
||||
0x02, 0x04, 0x04,
|
||||
};
|
||||
|
||||
static const u8 DQ_DQS_Table[] = {
|
||||
/* REG, VALUE */
|
||||
/* DRAM DQ/DQS Output Delay Control */
|
||||
0xdc, 0x65,
|
||||
0xdd, 0x01,
|
||||
0xde, 0xc0,
|
||||
/* DRAM DQ/DQS input Capture Control */
|
||||
0x78, 0x83,
|
||||
0x79, 0x83,
|
||||
0x7a, 0x00,
|
||||
};
|
||||
|
||||
static const u8 DQSOChA_DDR2_Driving_Table[] = {
|
||||
/* Rx70, Rx71 */
|
||||
/* DDRII533 1~2 rank */
|
||||
0x00, 0x01,
|
||||
/* DDRII533 3~4 rank */
|
||||
0x03, 0x00,
|
||||
/* DDRII400 1~2 rank */
|
||||
0x00, 0x04,
|
||||
/* DDRII400 3~4 rank */
|
||||
0x00, 0x01,
|
||||
};
|
||||
|
||||
/************************************************************************/
|
||||
/* Chipset Performance UP and other setting after DRAM Sizing Registers */
|
||||
/************************************************************************/
|
||||
static const u8 Dram_Table[] = {
|
||||
/* REG, AND, OR */
|
||||
0x60, 0xff, 0x03,
|
||||
0x66, 0xcf, 0x80,
|
||||
0x68, 0x00, 0x00,
|
||||
0x69, 0xfd, 0x03,
|
||||
0x6e, 0xff, 0x01,
|
||||
0x95, 0xff, 0x40,
|
||||
};
|
||||
|
||||
static const u8 Host_Table[] = {
|
||||
/* REG, AND, OR */
|
||||
0x51, 0x81, 0x7a,
|
||||
0x55, 0xff, 0x06,
|
||||
0x5e, 0x00, 0x88,
|
||||
0x5d, 0xff, 0xb2,
|
||||
};
|
||||
|
||||
static const u8 Init_Rank_Reg_Table[] = {
|
||||
/* Rank Ending Address Registers */
|
||||
0x40, 0x41, 0x42, 0x43,
|
||||
/* Rank Beginning Address Registers */
|
||||
0x48, 0x49, 0x4a, 0x4b,
|
||||
/* Physical-to-Virtual Rank Mapping Registers */
|
||||
0x54, 0x55,
|
||||
};
|
||||
|
||||
static const u16 DDR2_MRS_table[] = {
|
||||
/* CL: 2, 3, 4, 5 */
|
||||
0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */
|
||||
0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */
|
||||
};
|
||||
|
||||
#define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12))
|
||||
#define MRS_DDR2_TWR3 ((0 << 15) | (1 << 20) | (0 << 12))
|
||||
#define MRS_DDR2_TWR4 ((0 << 15) | (1 << 20) | (1 << 12))
|
||||
#define MRS_DDR2_TWR5 ((1 << 15) | (0 << 20) | (0 << 12))
|
||||
static const u32 DDR2_Twr_table[] = {
|
||||
MRS_DDR2_TWR2,
|
||||
MRS_DDR2_TWR3,
|
||||
MRS_DDR2_TWR4,
|
||||
MRS_DDR2_TWR5,
|
||||
};
|
||||
|
||||
static const u8 DQSI_Rate_Table[] = {
|
||||
8, /* DDRII 200 */
|
||||
8, /* DDRII 266 */
|
||||
8, /* DDRII 333 */
|
||||
7, /* DDRII 400 */
|
||||
8, /* DDRII 533 */
|
||||
8, /* DDRII 666 */
|
||||
};
|
||||
|
||||
static const u8 REFC_Table[] = {
|
||||
0x65, 0x32, /* DDRII 100 */
|
||||
0x86, 0x43, /* DDRII 266 */
|
||||
0xa8, 0x54, /* DDRII 333 */
|
||||
0xca, 0x65, /* DDRII 400 */
|
||||
0xca, 0x86, /* DDRII 533 */
|
||||
0xca, 0xa8, /* DDRII 666 */
|
||||
};
|
||||
|
||||
static void do_ram_command(const struct mem_controller *ctrl, u8 command)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue