riscv: Update register address

I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.

Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>

src/arch/riscv/virtual_memory.c

@@ -311,11 +311,10 @@ void mstatus_init(void)
 	set_csr(medeleg, delegate);
 
 	// Enable all user/supervisor-mode counters using
-	// v1.9.1 register addresses.
+	// v1.10 register addresses.
 	// They moved from the earlier spec.
 	// Until we trust our toolchain use the hardcoded constants.
 	// These were in flux and people who get the older toolchain
 	// will have difficult-to-debug failures.
-	write_csr(/*mucounteren*/0x320, 7);
-	write_csr(/*mscounteren*/0x321, 7);
+	write_csr(/*mcounteren*/0x306, 7);
 }