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riscv: Update register address 

I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.

Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
wxjstz 2017-06-06 16:50:46 +08:00 committed by Martin Roth
parent a57cc2ffb2
commit d277960eb8
1 changed files with 2 additions and 3 deletions
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5
src/arch/riscv/virtual_memory.c
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@ -311,11 +311,10 @@ void mstatus_init(void)
set_csr(medeleg, delegate); set_csr(medeleg, delegate);
// Enable all user/supervisor-mode counters using // Enable all user/supervisor-mode counters using
// v1.9.1 register addresses. // v1.10 register addresses.
// They moved from the earlier spec. // They moved from the earlier spec.
// Until we trust our toolchain use the hardcoded constants. // Until we trust our toolchain use the hardcoded constants.
// These were in flux and people who get the older toolchain // These were in flux and people who get the older toolchain
// will have difficult-to-debug failures. // will have difficult-to-debug failures.
write_csr(/*mucounteren*/0x320, 7); write_csr(/*mcounteren*/0x306, 7);
write_csr(/*mscounteren*/0x321, 7);
} }