mb/google/skyrim: First pass GPIO configuriation for Skyrim
BUG=b:214415401 TEST=builds BRANCH=none Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jon Murphy
Felix Held
parent
26f0310317
commit
d2873756a7
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@ -3,10 +3,142 @@
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* GPIO configuration in ramstage*/
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static const struct soc_amd_gpio base_gpio_table[] = {
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/* TODO: Fill gpio configuration */
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/* PWR_BTN_L */
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PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
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/* SYS_RESET_L */
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PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
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/* WAKE_L */
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PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
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/* SOC_PEN_DETECT_ODL */
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PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3),
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/* EN_PWR_FP */
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PAD_GPO(GPIO_4, HIGH),
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/* EN_PP3300_TCHPAD */
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PAD_GPO(GPIO_5, HIGH),
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/* SSD_AUX_RESET_L */
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PAD_GPO(GPIO_6, HIGH),
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/* WLAN_AUX_RST_L */
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PAD_GPO(GPIO_7, HIGH),
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/* EN_PWR_WWAN_X */
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PAD_GPO(GPIO_8, HIGH),
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/* EN_PP3300_WLAN */
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PAD_GPO(GPIO_9, HIGH),
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/* BT_DISABLE */
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PAD_GPO(GPIO_10, LOW),
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/* EC_SOC_WAKE_ODL */
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PAD_SCI(GPIO_11, PULL_NONE, EDGE_LOW),
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/* SOC_FP_RST_L */
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PAD_GPO(GPIO_12, LOW),
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/* GPIO_13 - GPIO_15: Not available */
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/* USB_OC0_L */
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PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
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/* SOC_SAR_INT_L */
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PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW),
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/* GSC_SOC_INT_L */
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PAD_GPI(GPIO_18, PULL_NONE),
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/* I2C3_SCL */
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PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
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/* I2C3_SDA */
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PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
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/* WLAN_DISABLE */
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PAD_GPO(GPIO_21, LOW),
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/* ESPI_ALERT_D1 */
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PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
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/* AC_PRES */
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PAD_NF(GPIO_23, AC_PRES, PULL_UP),
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/* SOC_FP_INT_L */
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PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
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/* GPIO_25: Not available */
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/* PCIE_RST0_L */
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PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
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/* SD_AUX_RESET_L */
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PAD_GPO(GPIO_27, HIGH),
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/* GPIO_28: Not available */
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/* EN_PP3300_TCHSCR */
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PAD_GPO(GPIO_29, HIGH),
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/* SOC_DISABLE_DISP_BL */
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PAD_GPO(GPIO_30, HIGH),
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/* Unused */
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PAD_NC(GPIO_31),
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/* LPC_RST_L */
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PAD_GPO(GPIO_32, LOW),
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/* GPIO_33 - GPIO_39: Not available */
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/* SOC_TCHPAD_INT_ODL */
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PAD_SCI(GPIO_40, PULL_NONE, EDGE_LOW),
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/* GPIO_41: Not available */
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/* WWAN_RST_L */
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PAD_GPO(GPIO_42, HIGH),
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/* GPIO_43 - GPIO_66: Not available */
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/* GPIO_67 */
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PAD_GPI(GPIO_67, PULL_NONE),
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/* SPI1_DATA2 */
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PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
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/* SPI1_DATA3 */
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PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
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/* ESPI_CS_L */
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PAD_NF(GPIO_74, SPI1_CS1_L, PULL_NONE),
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/* TCHSCR_REPORT_EN */
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PAD_GPO(GPIO_76, LOW),
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/* SPI1_CLK */
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PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
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/* EN_PP3300_CAM */
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PAD_GPO(GPIO_78, HIGH),
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/* SPI1_DATA1 */
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PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
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/* SPI1_DATA0 */
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PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
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/* EC_SOC_INT_ODL */
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PAD_GPI(GPIO_84, PULL_NONE),
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/* RAM_ID_1 / DEV_BEEP_DATA */
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PAD_GPI(GPIO_85, PULL_NONE),
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/* RAM_ID_2 / DEV_BEEP_LRCLK */
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PAD_GPI(GPIO_89, PULL_NONE),
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/* HP_INT_ODL */
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PAD_GPI(GPIO_90, PULL_NONE),
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/* RAM_ID_3 / DEV_BEEP_BCLK */
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PAD_GPI(GPIO_91, PULL_NONE),
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/* CLK_REQ0_L / SSD */
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PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
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/* I2C2_SCL */
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PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
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/* I2C2_SDA */
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PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
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/* CLK_REQ1_L / SD */
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PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
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/* CLK_REQ2_L / WLAN */
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PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
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/* SOC_FPMCU_BOOT0 */
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PAD_GPO(GPIO_130, LOW),
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/* TCHSCR_INT_ODL */
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PAD_GPI(GPIO_131, PULL_NONE),
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/* TCHSCR_RESET_L */
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PAD_GPO(GPIO_136, LOW),
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/* SOC_BIOS_WP_L */
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PAD_GPI(GPIO_138, PULL_NONE),
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/* EN_SPKR */
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PAD_GPO(GPIO_139, HIGH),
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/* RAM_ID_0 / DEV_BEEP_EN */
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PAD_GPI(GPIO_144, PULL_NONE),
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/* UART1_TXD / FP */
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PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
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/* UART0_RXD / DBG */
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PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
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/* UART1_RXD / FP*/
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PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
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/* UART0_TXD / DBG */
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PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
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/* I2C0_SCL */
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PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
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/* I2C0_SDA */
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PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
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/* I2C1_SCL */
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PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
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/* I2C1_SDA */
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PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
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};
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/* Early GPIO configuration in bootblock */
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